公开(公告)号：US20180069767A1

公开(公告)日：2018-03-08

申请号：US15257286

申请日：2016-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Joseph L. Greathouse ,  Guru Prasadh V. Venkataramani ,  Jan Vesely

IPC: H04L12/24 ,  H04L29/08 ,  G06F12/0817 ,  G06F9/50

CPC classification number: G06F12/0828 ,  G06F9/5011 ,  G06F9/5083 ,  G06F2209/504

Abstract: Techniques described herein improve processor performance in situations where a large number of system service requests are being received from other devices. More specifically, upon detecting that certain operating conditions that indicate a processor slowdown are present, the processor performs one or more system service adjustment techniques. These techniques include throttling (reducing the rate of handling) of such requests, coalescing (grouping multiple requests into a single group) the requests, disabling microarchitctural structures (such as caches or branch prediction units) or updates to those structures, and prefetching data for or pre-performing these requests. Each of these adjustment techniques helps to reduce the number of and/or workload associated with servicing requests for system services.