公开(公告)号：US20250004949A1

公开(公告)日：2025-01-02

申请号：US18217291

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Paul Blinzer ,  Anthony Asaro ,  Nippon HarshadKumar Raval ,  Anthony Thomas Gutierrez ,  Leopold Grinberg ,  Millind Mittal ,  Samuel Richard Bayliss

IPC: G06F12/1009 ,  G06F12/14

Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

公开(公告)号：US20240201993A1

公开(公告)日：2024-06-20

申请号：US18067506

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Leopold Grinberg

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/345 ,  G06F9/3877

Abstract: Data evaluation using processing-in-memory is described. In accordance with the described techniques, data evaluation logic is loaded into a processing-in-memory component. The processing-in-memory component executes the data evaluation logic to evaluate a minimum number of bits required to retrieve data from, or store data to, at least one memory location. A result is output indicating the number of bits required to represent data at the at least one memory location based on the evaluation.