公开(公告)号：US20200020384A1

公开(公告)日：2020-01-16

申请号：US16038738

申请日：2018-07-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Liang Zhao ,  YuBin Yao

IPC: G11C11/406 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/18

Abstract: In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.

公开(公告)号：US10593391B2

公开(公告)日：2020-03-17

申请号：US16038738

申请日：2018-07-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Liang Zhao ,  YuBin Yao

IPC: G11C11/406 ,  G06F13/18 ,  G06F13/16 ,  G11C11/4076

Abstract: In one form, a memory controller includes a command queue, an arbiter, a refresh logic circuit, and a final arbiter. The command queue receives and stores memory access requests for a memory. The arbiter selectively picks accesses from the command queue according to a first type of accesses and a second type of accesses. The first type of accesses and the second type of accesses correspond to different page statuses of corresponding memory accesses in the memory. The refresh logic circuit generates a refresh command to a bank of the memory and provides a priority indicator with the refresh command whose value is set according to a number of pending refreshes. The final arbiter selectively orders the refresh command with respect to memory access requests of the first type accesses and the second type accesses based on the priority indicator.