公开(公告)号：US10692545B2

公开(公告)日：2020-06-23

申请号：US16140356

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Milam Paraschou ,  Balwinder Singh ,  Gerald R. Talbot ,  Alushulla Jack Ambundo ,  Edoardo Prete ,  Thomas H. Likens, III ,  Michael A. Margules

IPC: G11C7/10 ,  G11C5/14 ,  G11C11/4074 ,  H04L25/02 ,  H03K17/687

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

公开(公告)号：US20200098399A1

公开(公告)日：2020-03-26

申请号：US16140356

申请日：2018-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Milam Paraschou ,  Balwinder Singh ,  Gerald R. Talbot ,  Alushulla Jack Ambundo ,  Edoardo Prete ,  Thomas H. Likens, III ,  Michael A. Margules

IPC: G11C5/14 ,  H03K17/687 ,  H04L25/02 ,  G11C11/4074

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.