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公开(公告)号：US20220309606A1
公开(公告)日：2022-09-29
申请号：US17214762
申请日：2021-03-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Pramod Vasant Argade , Martin G. Sarov , Milind N. Nemlekar
Abstract: Techniques for managing register allocation are provided. The techniques include detecting a first request to allocate first registers for a first wavefront; first determining, based on allocation information, that allocating the first registers to the first wavefront would result in a condition in which a deadlock is possible; in response to the first determining, refraining from allocating the first registers to the first wavefront; detecting a second request to allocate second registers for a second wavefront; second determining, based on the allocation information, that allocating the second registers to the second wavefront would result in a condition in which deadlock is not possible; and in response to the second determining, allocating the second registers to the second wavefront.
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公开(公告)号：US20220309125A1
公开(公告)日：2022-09-29
申请号：US17214779
申请日：2021-03-26
Applicant: Advanced Micro Devices, Inc.
IPC: G06F17/16 , G06F7/544 , G06F7/523 , H03K19/173
Abstract: A processing device is provided which comprises memory configured to store data and a processor. The processor comprises a plurality of MACs configured to perform matrix multiplication of elements of a first matrix and elements of a second matrix. The processor also comprises a plurality of logic devices configured to sum values of bits of product exponents values of the elements of the first matrix and second matrix and determine keep bit values for product exponents values to be kept for matrix multiplication. The processor also comprises a plurality of multiplexor arrays each configured to receive bits of the elements of the first matrix and the second matrix and the keep bit values and provide data for selecting which elements of the first matrix and the second matrix values are provided to the MACs for matrix multiplication.
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Patent Agency Ranking
公开(公告)号：US12067640B2
公开(公告)日：2024-08-20
申请号：US17214762
申请日：2021-03-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Pramod Vasant Argade , Martin G. Sarov , Milind N. Nemlekar
CPC classification number: G06T1/20 , G06F9/30105 , G06F9/3012 , G06F9/524 , G06T1/60
Abstract: Techniques for managing register allocation are provided. The techniques include detecting a first request to allocate first registers for a first wavefront; first determining, based on allocation information, that allocating the first registers to the first wavefront would result in a condition in which a deadlock is possible; in response to the first determining, refraining from allocating the first registers to the first wavefront; detecting a second request to allocate second registers for a second wavefront; second determining, based on the allocation information, that allocating the second registers to the second wavefront would result in a condition in which deadlock is not possible; and in response to the second determining, allocating the second registers to the second wavefront.
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公开(公告)号：US12072952B2
公开(公告)日：2024-08-27
申请号：US17214779
申请日：2021-03-26
Applicant: Advanced Micro Devices, Inc.
IPC: G06F17/16 , G06F7/523 , G06F7/544 , H03K19/173
CPC classification number: G06F17/16 , G06F7/523 , G06F7/5443 , H03K19/1737
Abstract: A processing device is provided which comprises memory configured to store data and a processor. The processor comprises a plurality of MACs configured to perform matrix multiplication of elements of a first matrix and elements of a second matrix. The processor also comprises a plurality of logic devices configured to sum values of bits of product exponents values of the elements of the first matrix and second matrix and determine keep bit values for product exponents values to be kept for matrix multiplication. The processor also comprises a plurality of multiplexor arrays each configured to receive bits of the elements of the first matrix and the second matrix and the keep bit values and provide data for selecting which elements of the first matrix and the second matrix values are provided to the MACs for matrix multiplication.
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公开(公告)号：US12197533B2
公开(公告)日：2025-01-14
申请号：US17214784
申请日：2021-03-26
Applicant: Advanced Micro Devices, Inc.
Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to receive a portion of data of a first matrix comprising a first plurality of elements and receive a portion of data of a second matrix comprising a second plurality of elements. The processor is also configured to determine values for a third matrix by dropping a number of products from products of pairs of elements of the first and second matrices based on approximating the products of the pairs of elements as a sum of the exponents of the pairs of elements and performing matrix multiplication on remaining products of the pairs of elements of the first and second matrices.
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公开(公告)号：US20220309126A1
公开(公告)日：2022-09-29
申请号：US17214784
申请日：2021-03-26
Applicant: Advanced Micro Devices, Inc.
Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to receive a portion of data of a first matrix comprising a first plurality of elements and receive a portion of data of a second matrix comprising a second plurality of elements. The processor is also configured to determine values for a third matrix by dropping a number of products from products of pairs of elements of the first and second matrices based on approximating the products of the pairs of elements as a sum of the exponents of the pairs of elements and performing matrix multiplication on remaining products of the pairs of elements of the first and second matrices.
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公开(公告)号：US20220103183A1
公开(公告)日：2022-03-31
申请号：US17032962
申请日：2020-09-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Pramod Vasant Argade , Swapnil P. Sakharshete , Daniel N. Peroni
IPC: H03M7/24
Abstract: Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.
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