-
公开(公告)号：US10248497B2
公开(公告)日：2019-04-02
申请号：US14521183
申请日：2014-10-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Prashant Jayaprakash Nair , David A. Roberts
Abstract: A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.
Search Results
1
records
(took 0.012 seconds)
筛选
AND
AND
过滤
NOT
NOT
Scan to Join
