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    SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUACTURING PROCESS
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUACTURING PROCESS 有权
    具有导电性和制造工艺的半导体器件

    公开(公告)号：US20140175663A1

    公开(公告)日：2014-06-26

    申请号：US13721599

    申请日：2012-12-20

    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

    Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

    Abstract translation: 根据本发明，提供一种半导体器件，其包括半导体管芯或芯片，封装主体和贯穿封装体通孔。 半导体芯片包括多个导电焊盘。 封装体封装半导体芯片的侧壁，并且具有形成在其中的至少一个孔，该孔具有规定的第一表面粗糙度值的侧壁。 贯穿封装主体通孔设置在封装主体的孔中，并且包括电介质材料和至少一个导电互连金属。 电介质材料设置在孔的侧壁上并且限定至少一个具有侧壁的孔，其具有小于第一表面粗糙度值的第二表面粗糙度值。 互连金属设置在孔内。

    SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUFACTURING PROCESS FOR SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUFACTURING PROCESS FOR SAME 审中-公开
    具有导通能力的半导体器件及其制造工艺

    公开(公告)号：US20160315052A1

    公开(公告)日：2016-10-27

    申请号：US15202350

    申请日：2016-07-05

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

    Abstract translation: 根据本发明，提供一种半导体器件，其包括半导体管芯或芯片，封装主体和贯穿封装体通孔。 半导体芯片包括多个导电焊盘。 封装体封装半导体芯片的侧壁，并且具有形成在其中的至少一个孔，该孔具有规定的第一表面粗糙度值的侧壁。 贯穿封装主体通孔设置在封装主体的孔中，并且包括电介质材料和至少一个导电互连金属。 电介质材料设置在孔的侧壁上并且限定至少一个具有侧壁的孔，其具有小于第一表面粗糙度值的第二表面粗糙度值。 互连金属设置在孔内。

    Semiconductor device having conductive via and manufacturing process
    4.
    发明授权
    Semiconductor device having conductive via and manufacturing process 有权
    具有导电通孔和制造工艺的半导体器件

    公开(公告)号：US09406552B2

    公开(公告)日：2016-08-02

    申请号：US13721599

    申请日：2012-12-20

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

    Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

    Abstract translation: 根据本发明，提供一种半导体器件，其包括半导体管芯或芯片，封装主体和贯穿封装体通孔。 半导体芯片包括多个导电焊盘。 封装体封装半导体芯片的侧壁，并且具有形成在其中的至少一个孔，该孔具有规定的第一表面粗糙度值的侧壁。 贯穿封装主体通孔设置在封装主体的孔中，并且包括电介质材料和至少一个导电互连金属。 电介质材料设置在孔的侧壁上并且限定至少一个具有侧壁的孔，其具有小于第一表面粗糙度值的第二表面粗糙度值。 互连金属设置在孔内。

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