公开(公告)号：US09437565B2

公开(公告)日：2016-09-06

申请号：US14586735

申请日：2014-12-30

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

Abstract translation: 本公开涉及包括半导体衬底，半导体芯片和导电材料的半导体封装结构。 半导体衬底包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入，并且包括至少一个焊盘。 导电凸块设置在至少一个垫上。 导电凸块的侧表面，至少一个焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 导电材料与导电凸块和半导体芯片电连接，导电材料的一部分设置在容纳空间中。

公开(公告)号：US09349611B2

公开(公告)日：2016-05-24

申请号：US13776567

申请日：2013-02-25

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L21/50 ,  H01L23/538 ,  H01L25/10 ,  H01L25/16 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Abstract translation: 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US09117697B2

公开(公告)日：2015-08-25

申请号：US14303371

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che Lee ,  Yuan-Chang Su ,  Wen-Chi Cheng ,  Guo-Cheng Liao ,  Yi-Chuan Ding

IPC: H01L23/52 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。

公开(公告)号：US09219048B2

公开(公告)日：2015-12-22

申请号：US14304528

申请日：2014-06-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yun-Hsiang Tien ,  Yi-Chuan Ding

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.

Abstract translation: 本公开提供了一种基板和半导体封装。 衬底包括主体，至少一个衬垫组，多个迹线和至少一个支柱组。 垫组包括多个垫。 每个垫具有至少一个内侧和至少一个外侧。 第一垫的内侧面相邻的第二垫的内侧，其间具有间隔开的部分。 每个支柱组包括设置在各个垫上的多个支柱。 使用具有多个焊盘以形成支柱的焊盘组允许增加给定区域中可用的支柱数量，以增加I / O连接量。 此外，对于给定数量的I / O连接，可以减少由焊盘，柱和迹线占据的面积。

公开(公告)号：US09960121B2

公开(公告)日：2018-05-01

申请号：US15202350

申请日：2016-07-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

公开(公告)号：US20140175663A1

公开(公告)日：2014-06-26

申请号：US13721599

申请日：2012-12-20

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

Abstract translation: 根据本发明，提供一种半导体器件，其包括半导体管芯或芯片，封装主体和贯穿封装体通孔。 半导体芯片包括多个导电焊盘。 封装体封装半导体芯片的侧壁，并且具有形成在其中的至少一个孔，该孔具有规定的第一表面粗糙度值的侧壁。 贯穿封装主体通孔设置在封装主体的孔中，并且包括电介质材料和至少一个导电互连金属。 电介质材料设置在孔的侧壁上并且限定至少一个具有侧壁的孔，其具有小于第一表面粗糙度值的第二表面粗糙度值。 互连金属设置在孔内。

公开(公告)号：US09978705B2

公开(公告)日：2018-05-22

申请号：US15222873

申请日：2016-07-28

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/48 ,  H01L23/00 ,  H05K3/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/20 ,  H05K3/46

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

公开(公告)号：US20160315052A1

公开(公告)日：2016-10-27

申请号：US15202350

申请日：2016-07-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

Abstract translation: 根据本发明，提供一种半导体器件，其包括半导体管芯或芯片，封装主体和贯穿封装体通孔。 半导体芯片包括多个导电焊盘。 封装体封装半导体芯片的侧壁，并且具有形成在其中的至少一个孔，该孔具有规定的第一表面粗糙度值的侧壁。 贯穿封装主体通孔设置在封装主体的孔中，并且包括电介质材料和至少一个导电互连金属。 电介质材料设置在孔的侧壁上并且限定至少一个具有侧壁的孔，其具有小于第一表面粗糙度值的第二表面粗糙度值。 互连金属设置在孔内。

公开(公告)号：US09406552B2

公开(公告)日：2016-08-02

申请号：US13721599

申请日：2012-12-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Jen Chen ,  Yi-Chuan Ding ,  Min-Lung Huang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.

Abstract translation: 根据本发明，提供一种半导体器件，其包括半导体管芯或芯片，封装主体和贯穿封装体通孔。 半导体芯片包括多个导电焊盘。 封装体封装半导体芯片的侧壁，并且具有形成在其中的至少一个孔，该孔具有规定的第一表面粗糙度值的侧壁。 贯穿封装主体通孔设置在封装主体的孔中，并且包括电介质材料和至少一个导电互连金属。 电介质材料设置在孔的侧壁上并且限定至少一个具有侧壁的孔，其具有小于第一表面粗糙度值的第二表面粗糙度值。 互连金属设置在孔内。