公开(公告)号：US20240371739A1

公开(公告)日：2024-11-07

申请号：US18144162

申请日：2023-05-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pin-Yao CHEN ,  Shiuan-Yu LIN ,  Hung-Jung TU

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: An electronic package includes a pad, a dielectric layer, a bump, and a conductive element. The dielectric layer encapsulates the pad and includes an opening exposing the pad. The bump is disposed over the pad. The conductive element is disposed in the opening between the pad and the bump. The conductive element is configured to mitigate a shrinkage of an electrical path between the pad and the bump occupied by an expansion of the dielectric layer.