公开(公告)号：US12099788B2

公开(公告)日：2024-09-24

申请号：US17296169

申请日：2019-11-25

Applicant: Agency for Science, Technology and Research

Inventor： Raju Salahuddin ,  Rahul Dutta ,  Kevin Tshun Chuan Chai ,  Ashish James ,  Chuan Sheng Foo ,  Zeng Zeng ,  Savitha Ramasamy ,  Vijay Ramaseshan Chandrasekhar

IPC: G06F30/27 ,  G06F30/31 ,  G06N20/00

CPC classification number: G06F30/27 ,  G06F30/31 ,  G06N20/00

Abstract: There is provided a method of predicting performance in electronic design based on machine learning using at least one processor, the method including: providing a first machine learning model configured to predict performance data for an electronic system based on a set of input design parameters for the electronic system; providing a second machine learning model configured to generate a new set of parameter values for the set of input design parameters for the electronic system based on a desired performance data provided for the electronic system; generating, using the second machine learning model, the new set of parameter values for the set of input design parameters for the electronic system based on the desired performance data provided for the electronic system; evaluating the set of input design parameters having the new set of parameter values for the electronic system to obtain an evaluated performance data associated with the set of input design parameters having the new set of parameter values; generating a new set of training data based on the set of input design parameters having the new set of parameter values and the evaluated performance data associated with the set of input design parameters having the new set of parameter values; and training the first machine learning model based on at least the new set of training data. There is also provided a corresponding system for predicting performance in electronic design based on machine learning.

公开(公告)号：US20220004900A1

公开(公告)日：2022-01-06

申请号：US17296169

申请日：2019-11-25

Applicant: Agency for Science, Technology and Research

Inventor： Raju Salahuddin ,  Rahul Dutta ,  Kevin Tshun Chuan Chai ,  Ashish James ,  Chuan Sheng Foo ,  Zeng Zeng ,  Savitha Ramasamy ,  Vijay Ramaseshan Chandrasekhar

IPC: G06N5/04 ,  G06N20/00 ,  G06F30/31

Abstract: There is provided a method of predicting performance in electronic design based on machine learning using at least one processor, the method including: providing a first machine learning model configured to predict performance data for an electronic system based on a set of input design parameters for the electronic system; providing a second machine learning model configured to generate a new set of parameter values for the set of input design parameters for the electronic system based on a desired performance data provided for the electronic system; generating, using the second machine learning model, the new set of parameter values for the set of input design parameters for the electronic system based on the desired performance data provided for the electronic system; evaluating the set of input design parameters having the new set of parameter values for the electronic system to obtain an evaluated performance data associated with the set of input design parameters having the new set of parameter values; generating a new set of training data based on the set of input design parameters having the new set of parameter values and the evaluated performance data associated with the set of input design parameters having the new set of parameter values; and training the first machine learning model based on at least the new set of training data. There is also provided a corresponding system for predicting performance in electronic design based on machine learning.

公开(公告)号：US20180102792A1

公开(公告)日：2018-04-12

申请号：US15568866

申请日：2016-05-05

Applicant: Agency for Science, Technology and Research

Inventor： Kheong Sann Chan ,  Ashish James

IPC: H03M13/41 ,  H03M13/29 ,  H03M13/00 ,  H04L1/00 ,  H04L25/03

CPC classification number: H03M13/41 ,  G11B2020/1863 ,  H03M13/29 ,  H03M13/6325 ,  H04L1/00 ,  H04L1/005 ,  H04L1/0054 ,  H04L1/006 ,  H04L25/03235

Abstract: According to various embodiments, a joint detector/decoder device may be provided. The joint detector/decoder device may include: an input circuit configured to receive an input signal; a splitting determination circuit configured to determine whether a survivor is to be split based on a parity check criterion; and a survivor splitting circuit configured to produce a plurality of survivors of a next instance based on at least one survivor of a previous instance and based on the input signal, if it is determined that the survivor of the previous instance is to be split; wherein each survivor has an associated bit sequence.