公开(公告)号：US20210396478A1

公开(公告)日：2021-12-23

申请号：US17286402

申请日：2018-10-17

Applicant: Agency for Science, Technology and Research ,  Singapore District Cooling Pte Ltd

Inventor： Wuhua HU ,  Chin Choy CHAI ,  Wenxian YANG ,  Rongshan YU

IPC: F28D20/02 ,  G06Q50/06 ,  G06Q10/04

Abstract: The present disclosure may provide a cooling plant system, a method of operating a cooling plant system and an energy storage and scheduling control system, the cooling plant system comprising one or more cooling towers; one or more thermal energy storage systems coupled to the one or more cooling towers; one or more electrical energy storage systems, the one or more electrical energy storage systems being coupled to the one or more thermal energy storage systems for selectively providing electrical energy to the one or more thermal energy storage systems; and an energy storage and scheduling control system coupled to the one or more thermal energy storage systems and the one or more electrical energy storage systems, the energy storage and scheduling control system being configured to control operations of the one or more thermal energy storage systems and the one or more electrical energy storage systems via a scheduling of the operations per time slot, the operations including the selective provision of electrical energy to the one or more thermal energy storage systems.

公开(公告)号：US20170169075A1

公开(公告)日：2017-06-15

申请号：US15121991

申请日：2015-03-02

Applicant: Agency for Science, Technology and Research

Inventor： Wenyu JIANG ,  Rongshan YU ,  Xiaoming BAO ,  Susanto RAHARDJA

IPC: G06F17/30 ,  G11C16/26 ,  G11C16/04 ,  G06F3/06

CPC classification number: G06F16/24569 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0679 ,  G11C13/0002 ,  G11C15/046 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: According to various embodiments, a testing apparatus may be provided. The testing apparatus may include: a cell pair comprising two l-bit memory cells configured to represent a stored pattern of l-bit; and a converter configured to convert a query pattern of l-bit into a pair of voltages defined such that when applied to gates of the cell pair, the voltages make the cell pair into high resistance mode when the query pattern matches the stored pattern and into low resistance mode when the query pattern does not match the stored pattern.