公开(公告)号：US20170169075A1

公开(公告)日：2017-06-15

申请号：US15121991

申请日：2015-03-02

Applicant: Agency for Science, Technology and Research

Inventor： Wenyu JIANG ,  Rongshan YU ,  Xiaoming BAO ,  Susanto RAHARDJA

IPC: G06F17/30 ,  G11C16/26 ,  G11C16/04 ,  G06F3/06

CPC classification number: G06F16/24569 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0679 ,  G11C13/0002 ,  G11C15/046 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: According to various embodiments, a testing apparatus may be provided. The testing apparatus may include: a cell pair comprising two l-bit memory cells configured to represent a stored pattern of l-bit; and a converter configured to convert a query pattern of l-bit into a pair of voltages defined such that when applied to gates of the cell pair, the voltages make the cell pair into high resistance mode when the query pattern matches the stored pattern and into low resistance mode when the query pattern does not match the stored pattern.