Abstract:
A charge redistribution SAR analog-to-digital converter includes a source of a reference voltage, a digital-to-analog converter, and a reset circuit. The digital-to-analog converter includes converter stages that range in significance from most significant to least significant. Each converter stage includes respective capacitors and switches. The switches are controllable to selectively connect the capacitors to the reference voltage or to ground. The capacitors of the converter stages are weighted in capacitance in accordance with significance of the converter stage. The reset circuit is to control the switches to reset the converter stages with a temporal offset between at least two of the converter stages. The temporal offset between the at least two of the converter stages reduces the dependence of the charge drawn from the reference voltage source during each conversion cycle on the sample of an analog input signal converted to a digital value during the conversion cycle.
Abstract:
A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.