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    ENVELOPE TRACKING POWER SUPPLY CIRCUIT AND HIGH-FREQUENCY AMPLIFIER INCLUDING ENVELOPE TRACKING POWER SUPPLY CIRCUIT
    2.
    发明申请
    ENVELOPE TRACKING POWER SUPPLY CIRCUIT AND HIGH-FREQUENCY AMPLIFIER INCLUDING ENVELOPE TRACKING POWER SUPPLY CIRCUIT 失效
    安全跟踪电源电路和高频放大器，包括环绕跟踪电源电路

    公开(公告)号：US20110031953A1

    公开(公告)日：2011-02-10

    申请号：US12866676

    申请日：2009-02-03

    申请人： Akihiro Kanbe ,  Masato Kaneta ,  Haruo Kobayashi ,  Hitoshi Hirata ,  Tatsuhiro Shimura

    发明人： Akihiro Kanbe ,  Masato Kaneta ,  Haruo Kobayashi ,  Hitoshi Hirata ,  Tatsuhiro Shimura

    IPC分类号： G05F3/02

    CPC分类号： H03F1/0227 ,  H02M2001/0045 ,  H03F3/189 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/195 ,  H03F2200/451 ,  Y02B70/1483

    摘要： The invention aims to maintain a high efficiency even for a high-frequency signal having a wideband envelope. The envelope tracking power supply circuit 5 is a power supply circuit for generating an output voltage according to the envelope of a high frequency signal and comprises a voltage follower circuit 7 for receiving an envelope signal and outputting a voltage according to the envelope signal SE; two parallel resistors Rsense connected in parallel between the output of the voltage follower circuit 7 and an output terminal PO; hysteresis comparators 9a, 9b for detecting respective voltage drops in the parallel resistors Rsense and generating voltages according to the voltage drops; and switching converters 11a, 11b for performing switching according to the respective voltages outputted from the hysteresis comparators 9a, 9b and outputting a voltage to the output terminal PO.

    摘要翻译： 本发明的目的在于即使对于具有宽带信封的高频信号也能保持高效率。 信封跟踪电源电路5是用于根据高频信号的包络产生输出电压的电源电路，并且包括用于接收包络信号并根据包络信号SE输出电压的电压跟随器电路7; 在电压跟随器电路7的输出端和输出端子PO之间并联连接的两个并联电阻器Rsense; 磁滞比较器9a，9b，用于检测并联电阻Rsense中的各个电压降，并根据电压降产生电压; 以及用于根据从迟滞比较器9a，9b输出的各个电压进行切换的开关转换器11a，11b，并向输出端子PO输出电压。

    Time-to-digital converter
    3.
    发明申请
    Time-to-digital converter 有权
    时间到数字转换器

    公开(公告)号：US20090225631A1

    公开(公告)日：2009-09-10

    申请号：US12382056

    申请日：2009-03-06

    申请人： Kazuya shimizu ,  Masato Kaneta ,  Haruo Kobayashi ,  Tatsuji Matsuura ,  Katsuyoshi Yagi ,  Akira Abe ,  Koichiro Mashiko

    发明人： Kazuya shimizu ,  Masato Kaneta ,  Haruo Kobayashi ,  Tatsuji Matsuura ,  Katsuyoshi Yagi ,  Akira Abe ,  Koichiro Mashiko

    IPC分类号： G04F10/00

    CPC分类号： G04F10/06

    摘要： A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

    摘要翻译： 公开了具有小尺度电路和高分辨率的TDC电路，其是检测相对于待测信号的参考时钟的相位的时间到数字转换器，包括第一延迟线，其中多个 具有第一延迟量的第一延迟元件被串联连接，第二延迟线组连接到第一延迟线的多个连接节点或第一级中的输入节点，并且其中至少一个或多个第二延迟 具有与第一延迟量不同的第二延迟量的元件串联连接;多个判断电路，用于判断待测信号的变化边沿是否相对于从...的延迟时钟输出的变化沿提前或延迟 第一延迟元件和第二延迟元件，以及操作电路，其从判断器计算相对于待测信号的变化边沿的参考时钟的相位 t结果，其中第一延迟量和第二延迟量之间的差小于第一延迟量和第二延迟量。

    Time-to-digital converter
    4.
    发明授权
    Time-to-digital converter 有权
    时间到数字转换器

    公开(公告)号：US07884751B2

    公开(公告)日：2011-02-08

    申请号：US12382056

    申请日：2009-03-06

    申请人： Kazuya Shimizu ,  Masato Kaneta ,  Haruo Kobayashi ,  Tatsuji Matsuura ,  Katsuyoshi Yagi ,  Akira Abe ,  Koichiro Mashiko

    发明人： Kazuya Shimizu ,  Masato Kaneta ,  Haruo Kobayashi ,  Tatsuji Matsuura ,  Katsuyoshi Yagi ,  Akira Abe ,  Koichiro Mashiko

    IPC分类号： H03M1/50

    CPC分类号： G04F10/06

    摘要： A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

    摘要翻译： 公开了具有小尺度电路和高分辨率的TDC电路，其是检测相对于待测信号的参考时钟的相位的时间到数字转换器，包括第一延迟线，其中多个 具有第一延迟量的第一延迟元件被串联连接，第二延迟线组连接到第一延迟线的多个连接节点或第一级中的输入节点，并且其中至少一个或多个第二延迟 具有与第一延迟量不同的第二延迟量的元件串联连接;多个判断电路，用于判断待测信号的变化边沿是否相对于从...的延迟时钟输出的变化沿提前或延迟 第一延迟元件和第二延迟元件，以及操作电路，其从判断器计算相对于待测信号的变化边沿的参考时钟的相位 t结果，其中第一延迟量和第二延迟量之间的差小于第一延迟量和第二延迟量。