摘要:
Methods and apparatus for producing a copper layer on substrate in a flat panel display manufacturing process, where the copper is electrodelessly deposited on a substrate to form a copper interconnection layer. A copper solution containing: CuSO4 5H2O as a copper source, potassium sodium tartrate or trisodium citrate as a complexing agent, glyoxylate, glyoxilic acid or sodium phosphate as a reducing agent, a sulfur organic compound as a stabilizing agent, and a pH adjusting agent, is used to form the copper interconnection layer on the substrate.
摘要翻译:在平板显示器制造工艺中在基板上制造铜层的方法和装置,其中铜无电极沉积在基板上以形成铜互连层。 作为铜源的包含CuSO 4 H 2 O 2 O 2的铜溶液,作为络合剂的酒石酸钾钠盐或柠檬酸钠盐,乙醛酸盐,乙氧基化磷酸盐或磷酸钠作为还原剂 作为稳定剂的硫有机化合物和pH调节剂,用于在基板上形成铜互连层。
摘要:
A method of depositing a copper interconnection layer on a substrate for use in a flat panel display interconnection system, comprising the steps of: a) coating said substrate with a photoresist layer; b) patterning said photoresist layer to obtain a patterned photoresist substrate comprising at least one trench patterned into said photoresist layer; c) providing a first catalyzation layer onto the patterned photoresist substrate; d) providing an electroless plated layer of an insulation layer deposited onto said first catalyzation layer; e) removing the successively superimposed photoresist layer, catalyzation layer and insulation layer except in the at least one trench, to obtain a pattern of the first catalyzation layer with an insulation layer deposited thereon.
摘要:
The invention is directed to a solar cell. The solar cell comprises a silicon layer, a front side electrode and a back side electrode. The silicon layer has a first surface and a second surface. The front side electrode is located on the first surface of the silicon layer. The back side electrode is located on the second surface of the silicon layer. Further, the back side electrode comprises a passivation layer, a first conductive layer and a second conductive layer. The passivation layer is located on the second surface of the silicon layer and has a plurality of holes penetrating through the passivation layer. The first conductive layer is located on the passivation layer and is electrically connected to the silicon layer through the holes. The second conductive layer is located on the first conductive layer.