公开(公告)号：US5144163A

公开(公告)日：1992-09-01

申请号：US631283

申请日：1990-02-20

申请人： Akira Matsuzawa ,  Shota Nakashima ,  Haruyasu Yamada

发明人： Akira Matsuzawa ,  Shota Nakashima ,  Haruyasu Yamada

IPC分类号： H03K19/0944 ,  H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/09448

摘要： A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

摘要翻译： 动态逻辑门包括用于与时钟同步地预充电逻辑门的预充电装置; 部分逻辑门被布置成使得根据逻辑输入的逻辑状态，允许电流在其两个端子之间流动或被切断; 其发射极接地的双极晶体管，以及用于在预充电期间内放电存储在双极晶体管的基极中的电荷的放电装置。 通过将部分逻辑门的导通电流提供给双极晶体管基极并使用双极晶体管的高速电流放大作用，逻辑门通过突然放电电路的负载能力来加速逻辑运算。

公开(公告)号：US5121002A

公开(公告)日：1992-06-09

申请号：US324038

申请日：1989-03-14

申请人： Akira Matsuzawa ,  Shota Nakashima ,  Haruyasu Yamada

发明人： Akira Matsuzawa ,  Shota Nakashima ,  Haruyasu Yamada

IPC分类号： H03K19/0944 ,  H03K19/096

CPC分类号： H03K19/09448 ,  H03K19/0963

摘要： A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

摘要翻译： 动态逻辑门包括用于与时钟同步地对逻辑门进行预充电的预充电装置; 部分逻辑门被布置成使得根据逻辑输入的逻辑状态，允许在其两个端子之间流动的电流或被切断; 发射极接地的双极晶体管，以及用于在预充电期间内放电存储在双极晶体管的基极中的电荷的放电装置。 通过将部分逻辑门的导通电流提供给双极晶体管基极并使用双极型晶体管的高速电流放大作用，逻辑门通过突然放电电路的负载能力来加速逻辑运算。

公开(公告)号：US20090292918A1

公开(公告)日：2009-11-26

申请号：US12097998

申请日：2006-12-15

申请人： Iichiro Mori ,  Shota Nakashima

发明人： Iichiro Mori ,  Shota Nakashima

IPC分类号： H04L9/32 ,  G06F21/20 ,  H04L9/08

CPC分类号： H04L63/0807 ,  G06F21/31 ,  G06F2221/2129 ,  H04L9/0891 ,  H04L9/0894 ,  H04L9/3271 ,  H04L2209/80

摘要： An authentication system is provided with a server device for generating a random number used for authentication and check data obtained by encrypting the random number using an encryption key, an authentication device for authenticating a device to be authenticated by transmitting the random number transmitted from the server device to the device to be authenticated and comparing reply data transmitted from the device to be authenticated with check data transmitted from the server device, and the device to be authenticated for encrypting the random number transmitted from the authentication device using the encryption key and transmitting the encrypted random number as reply data.

摘要翻译： 认证系统具有服务器装置，用于生成用于认证的随机数和使用加密密钥加密随机数获得的数据;认证装置，用于通过发送从服务器发送的随机数来认证要认证的设备 设备到要认证的设备，并且比较从要被认证的设备发送的应答数据与从服务器设备发送的检查数据，以及要认证的设备，用于加密使用加密密钥从认证设备发送的随机数，并发送 加密随机数作为答复数据。

公开(公告)号：US07113547B2

公开(公告)日：2006-09-26

申请号：US10223346

申请日：2002-08-20

申请人： Atsuo Inoue ,  Shota Nakashima

发明人： Atsuo Inoue ,  Shota Nakashima

IPC分类号： H04L27/00

CPC分类号： H04L25/45

摘要： In a controller device, when a first transmitting signal is at a “L” level, a first operation voltage is high and the amplitude of signals CK and ICK is large, and on the contrary, the amplitude is small when the first transmitting signal is at a “H” level. In a data carrier device, the signals CK and ICK are subjected to full-wave rectification by a rectifier circuit so as to generate a second operation voltage, and a first receiving signal is extracted from the second operation voltage by a first signal detection circuit. On the other hand, in the data carrier device, when a second transmitting signal is at a “L” level, impedance between two contacts is small and the amplitude of the signals CK and ICK is small, and on the contrary, the amplitude is large when the second transmitting signal is at a “H” level. In the controller device, change of the amplitude of the signal ICK is extracted as a second receiving signal by a second signal detection circuit. Accordingly, supply of power and clock and two-way serial data communication can be simultaneously executed between the controller device and the data carrier device through merely two contacts.

公开(公告)号：US07583734B2

公开(公告)日：2009-09-01

申请号：US10858388

申请日：2004-06-02

申请人： Shota Nakashima ,  Atsuo Inoue ,  Seizo Inagaki

发明人： Shota Nakashima ,  Atsuo Inoue ,  Seizo Inagaki

IPC分类号： H04L5/16

CPC分类号： H04L25/02 ,  H04L7/0008 ,  H04L25/08

摘要： When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

摘要翻译： 当控制器将正相的时钟脉冲作为第一发送信号（a）和相反相位的时钟脉冲作为第二发送信号（b）发送时，控制器将第二发送信号的“H”脉冲调制为 当发送数据的逻辑为“1”时，td1相对于第一发送信号的“L”脉冲的时间提前的信号，以及当传输数据的逻辑为“0”时与td2相对的时间提前的信号 “并发送调制信号。 数据载体装置通过使用从第一发送信号提取的时钟来检测第二发送信号的延迟时间的变化，以解调数据（e）。

公开(公告)号：US07307964B2

公开(公告)日：2007-12-11

申请号：US10274913

申请日：2002-10-22

申请人： Yuichiro Nakai ,  Shota Nakashima

发明人： Yuichiro Nakai ,  Shota Nakashima

IPC分类号： H04B7/212

CPC分类号： G06K7/0008 ,  G06K7/10039 ,  G06K19/0723

摘要： To provide a contactless communication system that can reduce a time required to complete an identification of all data carriers that exist around a reader/writer and thus attempt to speed up its processing. According to the contactless communication system, multiple data carriers detect a response requesting command from an access device and send back an individual response signal for one-bit information to the access device at a time that is ordered based on a portion of each carrier's identification information, and the access device monitors individual slots for the response signals and determines that detection of the presence of data carriers is completed when it has obtained individual signals from the data carriers, thereby reducing the time required to complete the identification of all data carriers.

摘要翻译： 提供一种非接触式通信系统，其可以减少完成识别存在于读写器周围的所有数据载体所需的时间，从而尝试加速其处理。 根据非接触式通信系统，多个数据载体检测来自接入设备的响应请求命令，并且在基于每个载波的识别信息的一部分排序的时间向接入设备发回一位信息的单独响应信号 ，并且接入设备监视响应信号的各个时隙，并确定当已经从数据载体获得各个信号时完成数据载波的存在的检测，从而减少完成所有数据载体的识别所需的时间。

公开(公告)号：US07055752B2

公开(公告)日：2006-06-06

申请号：US10030252

申请日：2001-05-21

申请人： Tetsuro Yoshimoto ,  Joji Katsura ,  Shota Nakashima ,  Takeshi Yamamoto ,  Miki Mizushima ,  Rie Ito

发明人： Tetsuro Yoshimoto ,  Joji Katsura ,  Shota Nakashima ,  Takeshi Yamamoto ,  Miki Mizushima ,  Rie Ito

IPC分类号： G06K19/06

CPC分类号： G06K7/0008 ,  G06K19/0723

摘要： A state control circuit gives an inactive state control signal to a CPU and an active state control signal to a data transmission circuit. In response to this, the CPU goes into the halt state and the data transmission circuit goes into the receive state. When receive processing is completed, the state control circuit gives an active state control signal to the CPU. In response to this, the CPU restores from the halt state to the operative state. The CPU gives an instruction signal to the state control circuit. The state control circuit gives an inactive state control signal to the data transmission circuit. In response to this, the data transmission circuit goes into the halt state.

摘要翻译： 状态控制电路向CPU发送非活动状态控制信号和向数据传输电路提供活动状态控制信号。 响应于此，CPU进入停止状态，数据发送电路进入接收状态。 当接收处理完成时，状态控制电路给CPU提供活动状态控制信号。 响应于此，CPU从停止状态恢复到操作状态。 CPU向状态控制电路发出指令信号。 状态控制电路向数据传输电路提供无效状态控制信号。 响应于此，数据传输电路进入停止状态。

公开(公告)号：US20050008080A1

公开(公告)日：2005-01-13

申请号：US10858388

申请日：2004-06-02

申请人： Shota Nakashima ,  Atsuo Inoue ,  Seizo Inagaki

发明人： Shota Nakashima ,  Atsuo Inoue ,  Seizo Inagaki

IPC分类号： H04L25/40 ,  H04B3/50 ,  H04L7/00 ,  H04L25/02 ,  H04L25/08 ,  H04L5/16

CPC分类号： H04L25/02 ,  H04L7/0008 ,  H04L25/08

摘要： To realize a stable communication without an erroneous data demodulation due to the influence of a skew between signals in a two-wire type data communication for performing a data communication and supplying clocks and electric power by first and second signal lines between a controller and a data storage device. When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

摘要翻译： 为了实现由于两线式数据通信中用于进行数据通信的信号之间的偏斜的影响并且由控制器和数据之间的第一和第二信号线提供时钟和电力而导致的错误数据解调的稳定通信 储存设备。 当控制器将正相的时钟脉冲作为第一发送信号（a）和相反相位的时钟脉冲作为第二发送信号（b）发送时，控制器将第二发送信号的“H”脉冲调制为 当发送数据的逻辑为“1”时，td1相对于第一发送信号的“L”脉冲的时间提前的信号，以及当传输数据的逻辑为“0”时与td2相对的时间提前的信号 “并发送调制信号。 数据载体装置通过使用从第一发送信号提取的时钟来检测第二发送信号的延迟时间的变化，以解调数据（e）。