Method of manufacturing semiconductor integrated circuit device
    2.
    发明授权
    Method of manufacturing semiconductor integrated circuit device 失效
    半导体集成电路器件的制造方法

    公开(公告)号:US06588005B1

    公开(公告)日:2003-07-01

    申请号:US09857771

    申请日:2001-06-11

    IPC分类号: G06F1500

    摘要: A wiring pattern is divided into sets of long wiring (L1) and sets of short wiring (Ls) by comparison to a reference value. Layout rules of the sets of long wiring (L1) are made different from layout rules of the sets of short wiring (Ls) by using an effect of a Levenson type phase shift. Thereby, an interval (S1) between a set of long wiring (L1) and a set of short wiring (Ls) is made relatively narrower than an interval (S2) between a set of long wiring (L1) and a set of long wiring (L1).

    摘要翻译: 与参考值相比,布线图案被分成长布线(L1)和短布线组(Ls)。 通过利用Levenson型相移的效果,使长布线组(L1)的布局规则与短布线组(Ls)的布局规则不同。 因此,一组长布线(L1)和一组短布线(Ls)之间的间隔(S1)比一组长布线(L1)和一组长布线之间的间隔(S2)相对窄 (L1)。