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公开(公告)号：US5629914A
公开(公告)日：1997-05-13
申请号：US407125
申请日：1995-03-20
IPC分类号： G11B7/0037 , G11B20/10 , G11B7/00
CPC分类号： G11B20/10203 , G11B20/10037 , G11B7/00375
摘要： In a pulse width modulated read signal channel for an optical disk drive, a data-transition threshold is maintained for data detection by a threshold tracking circuit that estimates the amplitude centerline data-transition threshold from the most recent maximum and minimum values of the read signal waveform. To improve the accuracy of the response of the centerline estimator, the threshold is increased or decreased based on the phase error at each read signal transition through the data-transition threshold. In addition, defects in the optical recording media are detected, and a defect present signal is used to inhibit the transition phase error input to the centerline estimator. This prevents the estimator from moving the threshold to an incorrect stable level. In addition, the defect present signal boosts the error feedback in the centerline estimator. The estimator then more quickly follows the read signal waveform. As a result, the estimator reacquires the centerline of the waveform after the read head moves past the defect without retriggering the defect detection circuit.
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公开(公告)号：US5502711A
公开(公告)日：1996-03-26
申请号：US407124
申请日：1995-03-20
IPC分类号： G11B7/005 , G11B11/105 , G11B20/14 , H03L7/07 , G11B7/00
CPC分类号： G11B20/1423 , H03L7/07 , G11B11/10515 , G11B7/005
摘要： A digital phase lock loop channel is provided for threshold detection of a pulse width modulated binary data stream that has negative and positive transitions defining one binary state of the data stream. A threshold-establishing and transition-detecting network receives this data stream and provides a first output of one polarity corresponding to the detection of a positive transition, a second output of an opposite polarity corresponding to the detection of a negative transition, and a time-of-arrival output corresponding to a positive and a negative transition. A first and a second digital PLL is provided, each PLL having a transition input, a time-of-arrival input, a phase-error input, a phase error output a data-valid output, and a data output. Each PLL has an internal digital phase detector network connected to receive its transition input and its time-of-arrival input, and each PLL is operable to generate the phase error output therefrom. Each PLL has an internal digital loop filter connected to receive the phase error output generated by its phase detector network, and to receive the phase error output that is generated by the other PLL. The output of the loop filter of each PLL is connected to the data-valid and data outputs of its respective PLL.
摘要翻译： 提供数字锁相环通道，用于阈值检测脉冲宽度调制二进制数据流，其具有定义数据流的一个二进制状态的负和正转换。 阈值建立和转移检测网络接收该数据流并且提供与正转移的检测相对应的一个极性的第一输出，对应于负转变检测的相反极性的第二输出， 到达输出对应于正和负转换。 提供第一和第二数字PLL，每个PLL具有转换输入，到达时间输入，相位误差输入，相位误差输出数据有效输出和数据输出。 每个PLL具有内部数字相位检测器网络，其连接以接收其转换输入及其到达时间输入，并且每个PLL可操作以从其产生相位误差输出。 每个PLL都有一个内部数字环路滤波器，用于接收相位检测器网络产生的相位误差输出，并接收由另一个PLL产生的相位误差输出。 每个PLL的环路滤波器的输出连接到其相应PLL的数据有效和数据输出。
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3.发明授权Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor 失效缓冲区用于在转移到第二处理器之前，从第一个处理器接收的不同大小和数据的数据块
公开(公告)号：US5117486A
公开(公告)日：1992-05-26
申请号：US341503
申请日：1989-04-21
IPC分类号： G06F15/16 , G06F13/38 , G06F13/40 , G06F15/173
CPC分类号： G06F13/4059
摘要： A bus-to-bus adapter is provided for coupling the input/output bus of a first data processor to the input/output bus of a second and different type of data processor. The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit and control logic for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.
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4.发明授权Programmable unit for controlling and interfacing of I/O busses of dissimilar data processing systems 失效用于控制和接口不同数据处理系统的I / O总线的可编程单元
公开(公告)号：US5581741A
公开(公告)日：1996-12-03
申请号：US341848
申请日：1994-11-16
CPC分类号： G06F13/4027
摘要： A programmable I/O bus adapter for interfacing and controlling two data processing systems having dissimilar and incompatible architectures. The programmable I/O bus adapter is capable of controlling the I/O bus and adapters of each of the two data processing systems. Simultaneously, the I/O bus adapter provides for interfacing and communication between the two dissimilar data processing systems. Interfacing from the bus adapter to each data processing system is provided by circuitry provided on integrated circuit chip sets specifically designed to interface with each system. The interfacing circuitry is enabled to convert signals between each system to allow for communication. Communication paths couple the adapter to the I/O bus of each system. The ability to access and control an I/O bus and adapter of each system is provided by a microprocessor having microcode instructions stored in programmable memory. The microcode provides for self-contained operation of the I/O bus adapter by enabling it to independently perform I/O control functions of the coupled systems. The microprocessor may be implemented by using a RISC architecture microprocessor device.
摘要翻译： 一种可编程I / O总线适配器，用于连接和控制具有不相似和不兼容架构的两个数据处理系统。 可编程I / O总线适配器能够控制两个数据处理系统中的每一个的I / O总线和适配器。 同时，I / O总线适配器提供两个不同数据处理系统之间的接口和通信。 从总线适配器到每个数据处理系统的接口由专门设计成与每个系统接口的集成电路芯片组上提供的电路提供。 接口电路能够在每个系统之间转换信号以允许通信。 通信路径将适配器连接到每个系统的I / O总线。 访问和控制每个系统的I / O总线和适配器的能力由具有存储在可编程存储器中的微代码指令的微处理器提供。 微代码通过使其独立地执行耦合系统的I / O控制功能来提供I / O总线适配器的独立操作。 微处理器可以通过使用RISC架构微处理器设备来实现。
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