公开(公告)号：US5623437A

公开(公告)日：1997-04-22

申请号：US532291

申请日：1995-09-22

申请人： Scott G. Nogle ,  Alan S. Roth

发明人： Scott G. Nogle ,  Alan S. Roth

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1051

摘要： A circuit having a combined level conversion and logic function (37, 90, 101, 102, and 103) receives a differential CMOS level input signal, and an input signal having a relatively small logic swing, performs a logic operation, and provides a single-ended CMOS output signal. The circuit (37) includes a CMOS switching portion (71) and a small signal switching portion (75) connected to provide a CMOS output signal that is the result of a logical operation of the input signals. The circuits (37, 90, 101, 102, and 103), eliminate the need for a separate level converter, reducing at least a gate delay, and insuring faster generation of the output signal. Also, the use of the circuit (37) having a combined level conversion and logic function allows the cache TAG (20) to provide read data at the same time that a match signal is generated.

摘要翻译： 具有组合电平转换和逻辑功能（37,90,101,102和103）的电路接收差分CMOS电平输入信号和具有相对小的逻辑摆幅的输入信号，执行逻辑运算，并提供单个 传输的CMOS输出信号。 电路（37）包括CMOS切换部分（71）和小信号切换部分（75），其连接以提供作为输入信号的逻辑运算结果的CMOS输出信号。 电路（37,90,101,102和103）消除了对单独的电平转换器的需要，至少减少门延迟，并确保更快地产生输出信号。 此外，具有组合电平转换和逻辑功能的电路（37）的使用允许高速缓存TAG（20）在产生匹配信号的同时提供读取数据。

公开(公告)号：US6011749A

公开(公告)日：2000-01-04

申请号：US49221

申请日：1998-03-27

申请人： Alan S. Roth ,  Scott G. Nogle

发明人： Alan S. Roth ,  Scott G. Nogle

IPC分类号： G11C7/22 ,  G11C8/00

CPC分类号： G11C7/22

摘要： An integrated circuit memory having a plurality of memory cells, output timing control means including frequency measurement means providing a frequency measurement count corresponding to a first frequency of the external clock signal and delay control means generating a delayed clock signal at the first frequency, wherein the delayed clock signal is delayed in time from the external clock signal in proportion to the first frequency, and data output control means outputting data from the plurality of memory cells responsive to the delayed clock signal. A method for adjusting output timing in a memory device including the steps of receiving an external clock signal, measuring a frequency of the external clock signal, generating a frequency count, determining an output delay proportional to the frequency, and generating an output clock at the external frequency and delayed from the external clock signal in proportion to the frequency.

摘要翻译： 一种具有多个存储单元的集成电路存储器，输出定时控制装置包括提供与外部时钟信号的第一频率相对应的频率测量计数的频率测量装置，以及以第一频率产生延迟时钟信号的延迟控制装置， 延迟时钟信号与第一频率成比例地从外部时钟信号延迟，并且数据输出控制装置响应于延迟的时钟信号从多个存储单元输出数据。 一种用于调整存储器件中的输出定时的方法，包括以下步骤：接收外部时钟信号，测量外部时钟信号的频率，产生频率计数，确定与频率成比例的输出延迟，以及在 外部频率和外部时钟信号与频率成比例延迟。

公开(公告)号：US5973955A

公开(公告)日：1999-10-26

申请号：US16940

申请日：1998-02-02

申请人： Scott G. Nogle ,  Alan S. Roth ,  Shuang L. Ho

发明人： Scott G. Nogle ,  Alan S. Roth ,  Shuang L. Ho

IPC分类号： G11C8/16 ,  G11C15/04 ,  G11C11/00

CPC分类号： G11C8/16 ,  G11C15/04

摘要： A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells. A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) uses both a differential amplifier (360) included within a D-flip-flop circuit (114) and a reference voltage provided by a reference voltage circuit (365) to compare addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

摘要翻译： 流水线双端口集成电路存储器（20）包括静态随机存取存储器（SRAM）单元的阵列（30）。 控制电路（32）控制对存储器单元的访问，其中基本同时的访问请求在正在访问存储器（20）的数据处理器的时钟信号的单个周期内被顺序地服务。 地址冲突检测器（110）使用包括在D触发器电路（114）内的差分放大器（360）和由参考电压电路（365）提供的参考电压来比较提供给两个端口的地址，以及 生成匹配信号，用于确定两个端口中的哪个端口首先被服务，独立于从哪个端口读取或写入。 由于使用单端口SRAM阵列（30）获得双端口功能，所以可以使用相对较少的集成电路表面积制造存储器（20），因此以较低的成本。

公开(公告)号：US5943274A

公开(公告)日：1999-08-24

申请号：US16914

申请日：1998-02-02

申请人： Alan S. Roth ,  Scott G. Nogle

发明人： Alan S. Roth ,  Scott G. Nogle

IPC分类号： G11C7/06 ,  G11C13/00

CPC分类号： G11C7/065

摘要： Method and apparatus for amplifying a signal (50) to produce a latched digital signal (46). In one embodiment, an output stage circuit (24) of memory (10) includes a differential amplifier circuit (100), a level converter (102), a timing circuit (104), a clock-free latch (106), a high impedance control circuit (108), a high impedance control circuit (110), and an output driver (112). Output stage (24) requires one clock signal to function. Alternate embodiments may skew the disabling edge of the clock to improve the speed characteristics of output stage (24). In one embodiment, signal (50) is a differential pair of signals provided from a memory bit cell array (12).

摘要翻译： 用于放大信号（50）以产生锁存数字信号（46）的方法和装置。 在一个实施例中，存储器（10）的输出级电路（24）包括差分放大器电路（100），电平转换器（102），定时电路（104），无时钟锁存器（106），高电平 阻抗控制电路（108），高阻抗控制电路（110）和输出驱动器（112）。 输出级（24）需要一个时钟信号来工作。 替代实施例可以使时钟的禁用边缘偏斜以改善输出级（24）的速度特性。 在一个实施例中，信号（50）是从存储器位单元阵列（12）提供的差分信号对。

公开(公告)号：US6078527A

公开(公告)日：2000-06-20

申请号：US103633

申请日：1998-06-23

申请人： Alan S. Roth ,  Scott George Nogle

发明人： Alan S. Roth ,  Scott George Nogle

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  G11C11/41

CPC分类号： G11C7/1072 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16

摘要： A pipelined dual port integrated circuit memory (20) includes an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.

摘要翻译： 流水线双端口集成电路存储器（20）包括静态随机存取存储器（SRAM）单元的阵列（21），其中每个存储单元（80）连接到单个字线（72）和单个位 线对（74,76）。 相对于相应的时钟信号，每个端口的访问是同步执行的。 两个时钟信号信号彼此是异步的。 当基本上同时从两个端口接收到访问请求时，仲裁电路（24）确定哪个端口接收优先权。 接收优先级的端口首先访问数组（21）。 仲裁电路（24）确保基本上同时的访问请求被顺序地服务并且在对应的时钟信号的单个周期内发生。

公开(公告)号：US5781480A

公开(公告)日：1998-07-14

申请号：US902009

申请日：1997-07-29

申请人： Scott George Nogle ,  Alan S. Roth ,  Shuang Li Ho

发明人： Scott George Nogle ,  Alan S. Roth ,  Shuang Li Ho

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  G11C11/41 ,  G11C16/04

CPC分类号： G11C8/16 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/22

摘要： A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

摘要翻译： 流水线双端口集成电路存储器（20）包括静态随机存取存储器（SRAM）单元的阵列（30），其中每个存储器单元（80）连接到单个字线（72）和单个位 线对（74,76）。 控制电路（32）控制对存储器单元的访问，其中基本同时的访问请求在正在访问存储器（20）的数据处理器的时钟信号的单个周期内被顺序地服务。 地址冲突检测器（110）比较提供给两个端口的地址，并且产生用于确定两个端口中的哪一个被首先服务的匹配信号，独立于从哪个端口读取或写入。 由于使用单端口SRAM阵列（30）获得双端口功能，所以可以使用相对较少的集成电路表面积制造存储器（20），因此以较低的成本。

公开(公告)号：US06504246B2

公开(公告)日：2003-01-07

申请号：US09415493

申请日：1999-10-12

申请人： Alan S. Roth ,  Jon D. Baney

发明人： Alan S. Roth ,  Jon D. Baney

IPC分类号： H01L2710

CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A balanced twist design for differential small signal pairs which is balanced in terms of resistance, capacitance and process variance. In the twist design of the present invention, each routing (6, 10) passes through two layers of metal. In addition, each routing (6, 10) passes through the same number of vias (9, 13, 14, 15), and experiences the same number of bends. Each routing (6, 10) is also exposed to the same sidewall crosstalk since the length and width of each routing (6, 10) in both metal layers is approximately the same. As a result, the new twist design reduces signal degradation, enhances signal separation, and allows increased clock speed of the integrated circuit.

摘要翻译： 用于差分小信号对的平衡扭曲设计，其在电阻，电容和工艺方差方面是平衡的。 在本发明的扭转设计中，每个布线（6,10）穿过两层金属。 此外，每个路由（6,10）通过相同数量的通孔（9,13,14,15），并且经历相同数量的弯曲。 每个路由（6,10）也暴露于相同的侧壁串扰，因为两个金属层中每个路由（6,10）的长度和宽度大致相同。 因此，新的扭曲设计降低了信号劣化，增强了信号分离，并且提高了集成电路的时钟速度。