公开(公告)号：US5706322A

公开(公告)日：1998-01-06

申请号：US439186

申请日：1995-05-11

申请人： Albert D. Scalo ,  Bruce F. Karaffa

发明人： Albert D. Scalo ,  Bruce F. Karaffa

IPC分类号： H03K23/00 ,  G04G3/02 ,  H03K21/16 ,  H03K23/40 ,  H03K23/50 ,  H03K21/40

CPC分类号： G04G3/02 ,  H03K21/16 ,  H03K23/50

摘要： A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.

摘要翻译： 以高达800MHz的频率工作的非常高速的计数器系统提供了时间测量，精度在（1 / f）秒的数量级，其中f是工作频率。 计数器的最低有效位以第一时钟信号的给定频率工作，而另一较高位在第二时钟信号下工作，其中第二时钟信号是第一时钟信号的频率的二分之一并被反相。 连接在第二计数器的级之间的进位先行电路与时钟方案一起操作以产生高速和精确的计数器。