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公开(公告)号：US07768480B2
公开(公告)日：2010-08-03
申请号：US11282112
申请日：2005-11-18
申请人： Makoto Onozawa , Tomokatsu Kishi , Hideaki Ohki , Masaki Kamada
发明人： Makoto Onozawa , Tomokatsu Kishi , Hideaki Ohki , Masaki Kamada
CPC分类号： G09G3/2965 , G09G3/292 , G09G3/2942 , G09G2310/0267 , G09G2310/061 , G09G2320/0252 , G09G2330/023
摘要： A problem is to be solved that there is to be provided a plasma display device capable of generating driving signals with less variation in delay time and without carrying out any phase adjustment. There is provided a plasma display device including; a first display electrode; a second display electrode adapted to cause a discharge to occur between the first display electrode and the second display electrode; a first display electrode drive circuit for applying a discharge voltage to the first display electrode; and a second display electrode drive circuit for applying a discharge voltage to the second display electrode. The first display electrode drive circuit has a first output element for supplying a first electric potential to the first display electrode in accordance with a first input signal which is inputted by using a transformer.
摘要翻译： 要解决的问题是要提供一种等离子体显示装置，能够产生延迟时间变化较小的驱动信号，而不进行任何相位调整。 提供了一种等离子体显示装置，包括： 第一显示电极; 适于在第一显示电极和第二显示电极之间产生放电的第二显示电极; 用于向第一显示电极施加放电电压的第一显示电极驱动电路; 以及用于向第二显示电极施加放电电压的第二显示电极驱动电路。 第一显示电极驱动电路具有用于根据通过使用变压器输入的第一输入信号向第一显示电极提供第一电位的第一输出元件。
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公开(公告)号：US5706322A
公开(公告)日：1998-01-06
申请号：US439186
申请日：1995-05-11
申请人： Albert D. Scalo , Bruce F. Karaffa
发明人： Albert D. Scalo , Bruce F. Karaffa
摘要： A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.
摘要翻译： 以高达800MHz的频率工作的非常高速的计数器系统提供了时间测量，精度在（1 / f）秒的数量级，其中f是工作频率。 计数器的最低有效位以第一时钟信号的给定频率工作，而另一较高位在第二时钟信号下工作，其中第二时钟信号是第一时钟信号的频率的二分之一并被反相。 连接在第二计数器的级之间的进位先行电路与时钟方案一起操作以产生高速和精确的计数器。
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公开(公告)号：US5428654A
公开(公告)日：1995-06-27
申请号：US257543
申请日：1994-06-09
申请人： Imran Baqai
发明人： Imran Baqai
CPC分类号： H03K23/56 , H03K23/005
摘要： An apparatus for counting occurrences of a particular input during a plurality of succeeding periods. The apparatus comprises an input terminal for receiving the input, a toggle signal generating circuit for generating a periodic toggle signal to mark the plurality of periods, and a plurality of n counter cell circuits for effecting the counting in n bits. Each counter cell circuit generates at least a respective bit output, a respective toggle output, and respective carry output. The counter cell circuits are arranged in hierarchical order from a least-significant counter cell circuit to a most-significant counter cell circuit. Each of the respective counter cell circuits is coupled with the next-most-significant counter cell circuit and provides the respective toggle output to the next-most-significant counter cell circuit as a respective toggle input, provides the respective carry/output to the next most-significant counter cell circuit as the respective carry input, except the most-significant counter cell circuit n receives its respective toggle input from the respective carry output of the twice-less-significant counter cell circuit cell circuit n-2.
摘要翻译： 一种用于在多个后续周期期间对特定输入的发生进行计数的装置。 该装置包括用于接收输入的输入端，用于产生用于标记多个周期的周期性触发信号的触发信号发生电路，以及用于以n位进行计数的多个n个计数单元电路。 每个计数器单元电路至少产生相应的位输出，相应的触发输出和相应的进位输出。 计数器单元电路以从最低有效计数单元电路到最有意义的计数单元电路的分级顺序排列。 每个相应的计数器单元电路与下一个最有意义的计数器单元电路耦合，并将相应的触发输出提供给下一个最有意义的计数器单元电路作为相应的触发输入，将相应的进位/输出提供给下一个 最有意义的计数器电路作为相应的进位输入，除了最有意义的计数单元电路n从两倍有效的计数单元电路单元电路n-2的相应进位输出端接收其各自的触发输入。
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4.发明授权High speed synchronous counter system and process with look-ahead carry generating circuit 失效高速同步计数器系统和具有前瞻进位发生电路的过程
公开(公告)号：US5062126A
公开(公告)日：1991-10-29
申请号：US498509
申请日：1990-03-26
申请人： Raymond G. Radys
发明人： Raymond G. Radys
摘要： High speed synchronous counters are constrained to operate within certain speeds due to delays inherent in the counter configurations. By utilizing look-ahead carries, that is, producing carry signals in anticipation of when they might be required, much of the delay can be eliminated. Speed performance can be further improved by fashioning the look-ahead carry system from programmable gate arrays, where non-standard logic structures can be created.
摘要翻译： 由于计数器配置固有的延迟，高速同步计数器被限制在一定速度内运行。 通过利用预先携带，即产生进位信号，以期可能需要它们，可以消除大部分的延迟。 可以通过从可编程门阵列形成先进的进位系统来进一步提高速度性能，可编程门阵列可以创建非标准逻辑结构。
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5.发明授权High speed counter with decoding means and means for selecting second and higher order counter stages to be toggled 失效具有解码装置的高速计数器和用于选择要切换的第二和更高阶计数器级的装置
公开(公告)号：US4669101A
公开(公告)日：1987-05-26
申请号：US806984
申请日：1985-12-16
申请人： Craig C. McCombs
发明人： Craig C. McCombs
摘要： A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse. The plurality of bistable devices, the decode section, and the select section operate in parallel with one another.
摘要翻译： 一个用于计数时钟脉冲并具有从第一输出位连续编号到最高输出位的多个输出位的计数器。 计数器包括多个双稳态器件，一个双稳态器件与每个输出位相关联，并且每个双稳态器件包括用于接收待计数的时钟脉冲的时钟输入和用于提供输出位及其补码之一的输出。 与第一输出位相关联的双稳态器件随着每个时钟脉冲的接收被切换以被计数。 计数器还包括响应多个双稳态器件的输出以提供解码信号的解码部分，以及用于接收待计数的时钟脉冲并响应于第一输出位的解码信号和补码的选择部分。 选择部分选择与第二和更高输出位相关联的多个双稳态器件中的哪一个将在接收到下一个时钟脉冲时切换。 多个双稳态装置，解码部分和选择部分彼此并行操作。
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6.发明授权Binary counter having buffer and coincidence circuits for the switched bistable stages thereof 失效具有用于其双稳态级的缓冲器和符合电路的二进制计数器
公开(公告)号：US4587665A
公开(公告)日：1986-05-06
申请号：US542195
申请日：1983-10-14
申请人： Hiroshi Minakuchi
发明人： Hiroshi Minakuchi
摘要： A binary counter consists of a plurality of unit stages each having a bistable circuit, a buffer circuit for generating an output corresponding to an output state of the bistable circuit, a switching circuit for supplying an output of the buffer circuit to the bistable circuit, and a coincidence gate for supplying a clock signal to the next unit stage in accordance with the predetermined output state of the bistable circuit.
摘要翻译： 二进制计数器包括多个单元级，每个单元级具有双稳态电路，用于产生对应于双稳态电路的输出状态的输出的缓冲电路，用于将缓冲电路的输出提供给双稳态电路的切换电路，以及 符合门，用于根据双稳态电路的预定输出状态向下一单元级提供时钟信号。
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公开(公告)号：US4431926A
公开(公告)日：1984-02-14
申请号：US331744
申请日：1981-12-17
申请人： Hiroshi Mayumi
发明人： Hiroshi Mayumi
CPC分类号： H03K5/15066 , G11C17/08 , G11C8/04 , H03K3/78 , H03K5/1502
摘要： A signal generator which may be fabricated as monolithic integrated circuit is disclosed. The signal generator includes a counter having a plurality of stages and providing parallel outputs and a plurality of flip-flops. A programmable logic array capable of functioning as AND and OR logic and composed of a matrix arrangement of programmable elements receives as inputs the parallel outputs of the counter and provides inputs to the flip-flops to generate signals at the outputs of the flip-flops.
摘要翻译： 公开了可制造为单片集成电路的信号发生器。 信号发生器包括具有多级的计数器并提供并行输出和多个触发器。 能够作为AND和OR逻辑并由可编程元件的矩阵布置组成的可编程逻辑阵列接收计数器的并行输出作为输入，并向触发器提供输入以在触发器的输出处产生信号。
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公开(公告)号：US4112429A
公开(公告)日：1978-09-05
申请号：US653793
申请日：1976-01-30
CPC分类号： H03K21/16 , G05B19/108 , G09G3/14 , H03K17/98 , H03K21/18 , G05B2219/23029 , G05B2219/23037
摘要： A contact responsive integrated switching and display system intended as an improvement to electromechanical devices such as rotary switches. The switching device controls the sequencing of displayed characters, by controlling gating of clock pulses into a counter, with activation of a function (such as selection of a circuit) corresponding to a selected displayed character produced by release of the switching device and discontinuance of the sequencing. The switching device is disclosed as physically directly associated or integrated with the display. The switch/display device can be self-contained or can be integrated in a system such as computer-data processing applications. An application of the device to data programming of a computer system is disclosed, in which a multidigit display is interfaced with a computer for operation in computer display, count advance and computer input modes. For each digit of the display, contact with the face of the display element gates clock pulses into a counter. The contents of the counter may be selectively displayed and/or output to the computer by way of a bidirectional data bus. The computer has a digit selection capability. The mode selection switch is implemented as a contact responsive visual display element.
摘要翻译： 接触式响应式集成开关和显示系统，旨在作为诸如旋转开关之类的机电装置的改进。 切换装置通过控制时钟脉冲门控到计数器来控制所显示字符的顺序，通过激活对应于由切换装置的释放产生的所选择的显示字符的功能（例如选择电路），并且断开 测序 公开了与显示器物理上直接相关联或集成的开关装置。 开关/显示设备可以是独立的或可以集成在诸如计算机数据处理应用的系统中。 公开了一种将该设备应用于计算机系统的数据编程的方法，其中，多计数显示器与计算机接口以在计算机显示，计数提前和计算机输入模式下操作。 对于显示器的每个数字，与显示元件的表面接触时钟脉冲进入计数器。 计数器的内容可以通过双向数据总线选择性地显示和/或输出到计算机。 计算机具有数字选择功能。 模式选择开关被实现为接触响应的视觉显示元件。
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公开(公告)号：US08498372B2
公开(公告)日：2013-07-30
申请号：US13129602
申请日：2009-11-24
申请人： Takashi Takeda
发明人： Takashi Takeda
CPC分类号： H03K23/662 , H03K23/44 , H03K23/58
摘要： A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode.
摘要翻译： 提供了可以通过简单的电路配置来切换延迟时间的计数器电路。 计数器电路包括级联连接的多级触发器，其中第一级中的触发器从作为输入信号的振荡器接收时钟，在第一级接收到第一级的触发器接收到Q 作为输入信号的前级，其中触发器的全部或部分全部或部分接收模式信号，并且其中多级触发器中的每一级将接收到的输入信号的频率除以2作为Q输出 当模式信号指示正常延迟模式时，并且当模式信号指示延迟缩短模式时，接收模式信号的触发器的每一级允许通过所接收的输入信号作为Q输出输出。
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公开(公告)号：US20110058639A1
公开(公告)日：2011-03-10
申请号：US12629889
申请日：2009-12-03
申请人： JIN-LIANG XIONG
发明人： JIN-LIANG XIONG
摘要： A counting apparatus includes a sampling circuit, and a counting and displaying circuit. The sampling circuit includes an interface, a first electric switch, and a second electric switch. The counting and displaying circuit includes a counter and a display tube. Seven input terminals of the display tube are connected to seven output terminals of the counter correspondingly. A clock-up counting terminal of the counter is connected to the second terminal of the second electric switch.
摘要翻译： 计数装置包括采样电路和计数显示电路。 采样电路包括接口，第一电开关和第二电开关。 计数显示电路包括计数器和显示管。 显示管的七个输入端子相应地连接到计数器的七个输出端子。 计数器的时钟计数端子连接到第二电开关的第二端子。
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