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公开(公告)号：US20120249213A1
公开(公告)日：2012-10-04
申请号：US13075652
申请日：2011-03-30
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译： 在集成电路中实现交流电源门控的结构和方法。 半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。 每个相应的一个功率门开关由使能信号中的相应一个使能。 交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。
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公开(公告)号：US20130275821A1
公开(公告)日：2013-10-17
申请号：US13445187
申请日：2012-04-12
申请人： George M. BRACERAS , Albert M. CHU , Kevin W. Gorman , Michael R. OUELLETTE , Ronald A. PIRO , Daryl M. SEITZER , Rohit SHETTY , Thomas W. WYCKOFF
发明人： George M. BRACERAS , Albert M. CHU , Kevin W. Gorman , Michael R. OUELLETTE , Ronald A. PIRO , Daryl M. SEITZER , Rohit SHETTY , Thomas W. WYCKOFF
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译： 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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3.发明申请SYSTEMS AND METHODS FOR DETERMINING ADJUSTABLE WAFER ACCEPTANCE CRITERIA BASED ON CHIP CHARACTERISTICS 有权用于基于芯片特性确定可调节波形接受标准的系统和方法公开(公告)号：US20120310574A1
公开(公告)日：2012-12-06
申请号：US13151337
申请日：2011-06-02
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics. The method includes measuring a density of at least one chip. The method further includes computing a difference in density between the density of the at least one chip and a density of at least one kerf structure. The method further includes calculating an offset value to modify a Wafer Acceptance Criteria (WAC) to match the density difference between the at least one chip and the at least one kerf structure. The method further includes applying the offset value to the WAC for a wafer level measurement in order to increase chip yield performance.
摘要翻译： 基于芯片特性确定可调晶片接收标准的系统和方法。 该方法包括测量至少一个芯片的密度。 该方法还包括计算至少一个芯片的密度与至少一个切口结构的密度之间的密度差。 该方法还包括计算偏移值以修改晶片验收标准（WAC）以匹配至少一个芯片和至少一个切口结构之间的密度差。 该方法还包括将偏移值应用于晶片级测量的WAC以提高芯片产量性能。
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4.发明申请公开(公告)号：US20130239078A1
公开(公告)日：2013-09-12
申请号：US13416015
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.
摘要翻译： 提供系统和方法以通过调节系统过程变化来优化关键路径，例如IC设计中的区域时序变化。 一种方法包括在关键路径内确定半导体芯片设计中的元件的物理位置。 该方法还包括基于与元件相关联的多晶硅导体周长密度来调制半导体芯片设计的系统过程变化以加速关键路径。
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