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1.发明授权Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics 有权基于芯片特性确定可调晶片接收标准的系统和方法公开(公告)号：US08862417B2
公开(公告)日：2014-10-14
申请号：US13151337
申请日：2011-06-02
CPC分类号： H01L22/20 , H01L22/12 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics. The method includes measuring a density of at least one chip. The method further includes computing a difference in density between the density of the at least one chip and a density of at least one kerf structure. The method further includes calculating an offset value to modify a Wafer Acceptance Criteria (WAC) to match the density difference between the at least one chip and the at least one kerf structure. The method further includes applying the offset value to the WAC for a wafer level measurement in order to increase chip yield performance.
摘要翻译： 基于芯片特性确定可调晶片接收标准的系统和方法。 该方法包括测量至少一个芯片的密度。 该方法还包括计算至少一个芯片的密度与至少一个切口结构的密度之间的密度差。 该方法还包括计算偏移值以修改晶片验收标准（WAC）以匹配至少一个芯片和至少一个切口结构之间的密度差。 该方法还包括将偏移值应用于晶片级测量的WAC以提高芯片产量性能。
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2.发明申请SYSTEMS AND METHODS FOR DETERMINING ADJUSTABLE WAFER ACCEPTANCE CRITERIA BASED ON CHIP CHARACTERISTICS 有权用于基于芯片特性确定可调节波形接受标准的系统和方法公开(公告)号：US20120310574A1
公开(公告)日：2012-12-06
申请号：US13151337
申请日：2011-06-02
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/12 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics. The method includes measuring a density of at least one chip. The method further includes computing a difference in density between the density of the at least one chip and a density of at least one kerf structure. The method further includes calculating an offset value to modify a Wafer Acceptance Criteria (WAC) to match the density difference between the at least one chip and the at least one kerf structure. The method further includes applying the offset value to the WAC for a wafer level measurement in order to increase chip yield performance.
摘要翻译： 基于芯片特性确定可调晶片接收标准的系统和方法。 该方法包括测量至少一个芯片的密度。 该方法还包括计算至少一个芯片的密度与至少一个切口结构的密度之间的密度差。 该方法还包括计算偏移值以修改晶片验收标准（WAC）以匹配至少一个芯片和至少一个切口结构之间的密度差。 该方法还包括将偏移值应用于晶片级测量的WAC以提高芯片产量性能。
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3.发明授权公开(公告)号：US08726210B2
公开(公告)日：2014-05-13
申请号：US13416015
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.
摘要翻译： 提供系统和方法以通过调节系统过程变化来优化关键路径，例如IC设计中的区域时序变化。 一种方法包括在关键路径内确定半导体芯片设计中的元件的物理位置。 该方法还包括基于与元件相关联的多晶硅导体周长密度来调制半导体芯片设计的系统过程变化以加速关键路径。
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4.发明申请ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN FOR ATTAINING POWER CLOSURE WHILE MAINTAINING EXISTING DESIGN CONSTRAINTS 失效集成电路设计的迭代合成，用于在维护现有设计约束的情况下进行电源关闭公开(公告)号：US20080307383A1
公开(公告)日：2008-12-11
申请号：US11759332
申请日：2007-06-07
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译： 描述了迭代地合成集成电路设计以获得功率闭合的方法。 在一个实施例中，集成电路设计最初被合成以满足定时和功率约束。 将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。 电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。 一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。
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5.发明申请DESIGN SYSTEM AND METHOD THAT, DURING TIMING ANALYSIS, COMPENSATES FOR REGIONAL TIMING VARIATIONS 审中-公开设计系统和方法，在时序分析期间，用于区域时间变化的补偿公开(公告)号：US20110107291A1
公开(公告)日：2011-05-05
申请号：US12612909
申请日：2009-11-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths.
摘要翻译： 公开了允许在定时分析期间补偿区域时间变化的实施例，并且可选地允许优化关键路径的放置，作为这种区域时序变化的函数。 基于用于集成电路芯片的器件的初始放置，映射影响器件定时的一个或多个物理条件（例如，多晶硅周长密度，器件到阱边缘的平均距离，平均反射率）的区域变化。 然后，使用将不同降额因子与不同级别的物理条件相关联的表，将降额因子分配给地图上的不同区域。 接下来，进行定时分析，使得对于每个区域，该区域内的任何路径的延迟被降低了所指定的降额因子。 当在集成电路芯片上建立设备的最终放置以便优化关键路径的放置时，也可以使用地图信息。
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6.发明授权Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints 失效集成电路设计的迭代合成，用于实现电源关闭，同时保持现有的设计约束公开(公告)号：US07539968B2
公开(公告)日：2009-05-26
申请号：US11759332
申请日：2007-06-07
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译： 描述了迭代地合成集成电路设计以获得功率闭合的方法。 在一个实施例中，集成电路设计最初被合成以满足定时和功率约束。 将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。 电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。 一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。
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7.发明授权Design structure for performing iterative synthesis of an integrated circuit design to attain power closure 有权用于执行集成电路设计的迭代合成以实现功率闭合的设计结构公开(公告)号：US07886253B2
公开(公告)日：2011-02-08
申请号：US11872731
申请日：2007-10-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译： 描述了执行集成电路设计的迭代合成以实现功率闭合的设计结构。 在一个实施例中，设计结构体现在计算机可读介质中，并具有初始合成集成电路设计以满足定时和功率约束的能力。 将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。 电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。 一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。
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公开(公告)号：US07873923B2
公开(公告)日：2011-01-18
申请号：US12038845
申请日：2008-02-28
CPC分类号： G06F17/505 , G06F2217/78
摘要： Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.
摘要翻译： 描述了电源门控逻辑锥。 在一个实施例中，一种方法包括用于集成电路（IC）设计的合成逻辑; 识别切换小于阈值的逻辑内的低交换节点; 基于所识别的低交换节点确定潜在功率门控锥（PGC）; 确定潜在PGC的功率选通逻辑表达式，其包括对最不切换的电位PGC的最小输入集合; 确定使用电源门控逻辑表达式的节能是否符合标准; 并接受潜在的PGC以满足标准。
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9.发明申请STRUCTURE FOR PERFORMING ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN TO ATTAIN POWER CLOSURE 有权用于执行集成电路设计的迭代合成以实现电源闭合的结构公开(公告)号：US20090100398A1
公开(公告)日：2009-04-16
申请号：US11872731
申请日：2007-10-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated circuit design to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译： 描述了执行集成电路设计的迭代合成以实现功率闭合的设计结构。 在一个实施例中，设计结构体现在计算机可读介质中，并具有初始合成集成电路设计以满足定时和功率约束的能力。 将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。 电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。 一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。
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公开(公告)号：US20090222772A1
公开(公告)日：2009-09-03
申请号：US12038845
申请日：2008-02-28
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.
摘要翻译： 描述了电源门控逻辑锥。 在一个实施例中，一种方法包括用于集成电路（IC）设计的合成逻辑; 识别切换小于阈值的逻辑内的低交换节点; 基于所识别的低交换节点确定潜在功率门控锥（PGC）; 确定潜在PGC的功率选通逻辑表达式，其包括对最不切换的电位PGC的最小输入集合; 确定使用电源门控逻辑表达式的节能是否符合标准; 并接受潜在的PGC以满足标准。
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