公开(公告)号：US20050022145A1

公开(公告)日：2005-01-27

申请号：US10924531

申请日：2004-08-23

申请人： Alexander Tetelbaum ,  Maad Al-Dabagh

发明人： Alexander Tetelbaum ,  Maad Al-Dabagh

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/50

摘要： A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.

摘要翻译： 一种用于在集成电路设计中查找定时关键网络的方法和计算机程序产品包括以下步骤：（a）接收集成电路设计作为输入; （b）计算集成电路设计中每个网络的近似延迟，其中近似延迟包括串扰延迟的估计; （c）从集成电路设计中每个网络的计算延迟识别定时关键网; （d）计算每个定时关键网络的对应精确延迟; （e）用相应的精确延迟代替每个定时关键网计算的近似延迟，以产生用于集成电路设计的校正的一组净延迟; 和（f）产生用于集成电路设计的校正的一组净延迟的输出。

公开(公告)号：US20130080986A1

公开(公告)日：2013-03-28

申请号：US13246102

申请日：2011-09-27

申请人： Alexander Tetelbaum ,  Hyuk-Jong Yi

发明人： Alexander Tetelbaum ,  Hyuk-Jong Yi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.

摘要翻译： 执行静态时序分析的系统和方法。 在一个实施例中，该系统包括：（1）CVS工具，被配置为在集成电路设计中确定与多个单元中的每一个相对应的基于单元的电压供应;以及（2）STA工具，被配置为将 基于相应的基于电池的电源。

公开(公告)号：US20090282381A1

公开(公告)日：2009-11-12

申请号：US12248016

申请日：2008-10-08

申请人： Alexander Tetelbaum ,  Sreejit Chakravarty

发明人： Alexander Tetelbaum ,  Sreejit Chakravarty

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

摘要： An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

摘要翻译： 用于优化集成电路（IC）中过程监视器（PM）的放置的电子设计自动化（EDA）工具和方法。 在一个实施例中，EDA工具包括：（1）关键路径/小区标识符，被配置为识别IC中的关键路径和关键小区，（2）候选PM位置标识符，其耦合到关键路径/小区标识符并且被配置为识别 一组PM的候选位置，（3）耦合到关键路径/小区标识符并被配置为将关键小区相关联以形成其簇的簇生成器和（4）耦合到候选PM位置标识符的PM布局优化器，以及 所述簇生成器并且被配置为通过在所述候选位置之中选择来将PM放置在每个所述簇内。

公开(公告)号：US20070079274A1

公开(公告)日：2007-04-05

申请号：US11244486

申请日：2005-10-05

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function of content of each of the separate routing rules, and generating as output the combined routing rule and a routing rule assignment that assigns the combined routing rule to the net.

摘要翻译： 路由集成电路设计的方法包括以下步骤：接收作为输入的集成电路设计的至少一部分，包括分配给同一网络的至少两个分离的路由规则以路由集成电路设计，制定单个组合路由规则作为 每个单独的路由规则的内容的功能，以及将组合路由规则和将组合路由规则分配给网络的路由规则分配生成输出。

公开(公告)号：US20060294482A1

公开(公告)日：2006-12-28

申请号：US11165778

申请日：2005-06-24

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net comprising a net cell and a net interconnect in an integrated circuit design; providing a worst case margin multiplier and a best case margin multiplier for the integrated circuit design; calculating a worst case minimum net interconnect delay from the worst case maximum net interconnect delay, the coupling capacitance, the net capacitance, and the worst case margin multiplier when the worst case maximum net interconnect delay is provided; and calculating a best case maximum net interconnect delay from the best case minimum net interconnect delay, the net capacitance, and the best case margin multiplier when the best case minimum net interconnect delay is provided.

摘要翻译： 提供节省运行时间以节省串扰的网络延迟的方法和计算机程序产品包括提供耦合电容，净电容以及最坏情况下最大网互连延迟和最佳情况下最小网互连之一的步骤 在集成电路设计中包括网络单元和网络互连的网络的延迟; 为集成电路设计提供最坏情况的边际倍数和最佳情况裕量倍增器; 当最坏情况下最大净互连延迟提供时，从最坏情况最大净互连延迟，耦合电容，净电容和最差情况裕量乘数计算最坏情况最小净互连延迟; 并且当提供最佳情况下最小净互连延迟时，从最佳情况下最小净互连延迟，净电容和最佳情况裕量乘数计算最佳情况下最大网互连延迟。

公开(公告)号：US20050060675A1

公开(公告)日：2005-03-17

申请号：US10665927

申请日：2003-09-17

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A method of noise analysis and correction of noise violations for an integrated circuit design includes steps of (a) receiving as input a standard parasitic exchange file for an integrated circuit design; (b) parsing the standard parasitic exchange file to generate a resistance graph; (c) generating a representation of the resistance graph to determine noise critical nets; (d) generating a list of only noise critical nets from the representation of the resistance graph; (e) selecting a net from the list of only noise critical nets; (f) calculating a value of total crosstalk noise in the selected net from all aggressor nets relative to the selected net; and (g) generating as output the value of total crosstalk noise in the selected net for correcting a noise violation.

摘要翻译： 用于集成电路设计的噪声分析和噪声违规校正的方法包括以下步骤：（a）作为输入接收用于集成电路设计的标准寄生交换文件; （b）解析标准寄生交换文件以生成电阻图; （c）生成电阻图的表示以确定噪声关键网; （d）从电阻图的表示中产生仅噪声关键网的列表; （e）从唯一的噪音关键网列表中选择一个网络; （f）从所有侵略者网络相对于所选择的网络计算所选网络中的总串扰噪声值; 以及（g）产生用于校正噪声冲突的所选网络中的总串扰噪声的值作为输出。

公开(公告)号：US20050050497A1

公开(公告)日：2005-03-03

申请号：US10650296

申请日：2003-08-27

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/62

摘要： A method of cell placement and clock tree synthesis includes steps of: (a) identifying critical paths in an integrated circuit design; (b) partitioning the integrated circuit design into a timing group for each of the critical paths; (c) assigning each flip-flop in a critical path to a timing group corresponding to the critical path; (d) performing a cell placement to minimize a function of propagation delay and maximum distance between flip-flops within each timing group; and (e) constructing a clock sub-net for each timing group.

摘要翻译： 一种单元布置方法和时钟树合成方法包括以下步骤：（a）识别集成电路设计中的关键路径; （b）将集成电路设计分成用于每个关键路径的定时组; （c）将关键路径中的每个触发器分配给对应于关键路径的定时组; （d）执行单元放置以最小化每个定时组内的触发器之间的传播延迟和最大距离的功能; 和（e）为每个定时组构建时钟子网。

公开(公告)号：US06543038B1

公开(公告)日：2003-04-01

申请号：US09771272

申请日：2001-01-26

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method for calculating skew associated with providing a signal to a capacitive load along a first and second wire. The method includes steps of calculating a skew error which would result if the Elmore Model were used to calculate delays using the actual length of the wires, calculating a new effective length for the second wire based on the error which has been calculated, using the Elmore Model to calculate an effective delay which would be associated with providing the signal to the capacitive load along the new effective length of wire, and calculating skew using the effective delay which has been calculated. Preferably, the new effective length for the second wire is calculated by considering the actual lengths of the first and second wires, the capacitance of a unit length of wire and the capacitance of the capacitive load.

摘要翻译： 一种用于计算与沿着第一和第二线向容性负载提供信号相关联的偏斜的方法。 该方法包括计算偏差误差的步骤，如果Elmore模型用于使用导线的实际长度来计算延迟，则将使用Elmore模型计算出偏斜误差，基于已计算的误差，使用Elmore计算第二导线的新有效长度 用于计算有效延迟的模型，其将与沿着新的有效长度的线提供信号到电容性负载相关联，并且使用已经计算的有效延迟计算偏差。 优选地，通过考虑第一和第二线的实际长度，线的单位长度的电容和电容性负载的电容来计算第二线的新的有效长度。

公开(公告)号：US08645888B2

公开(公告)日：2014-02-04

申请号：US13453289

申请日：2012-04-23

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F2217/84

摘要： Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.

摘要翻译： 提供了用于提高包括单元库中的至少一个单元的电路的定时表征精度的方法和装置。 一种方法包括以下步骤：为规定的第一和第二温度执行小区的小区库定时表征，第一和第二温度分别对应于电路的最小和最大运行温度; 选择第一和第二温度之间的一个或多个附加温度; 在一个或多个附加温度以及在第一和第二温度下对每个过程，电压和温度（PVT）角进行电池定时表征; 并且使用所述一个或多个附加温度对每个PVT角执行定时签出，所述定时签发至少部分地基于每个PVT角的时序表征。

公开(公告)号：US08539424B2

公开(公告)日：2013-09-17

申请号：US13058176

申请日：2008-08-14

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.

摘要翻译： 一种用于设计电路的设计过程优化系统和方法，其可以是采用自适应电压和缩放优化（AVSO）的集成电路（IC）。 在一个实施例中，系统包括：（1）过程电压 - 温度（PVT）库数据库，被配置为包含要由其构建电路的单元的PVT​​特性的PVT库，以及（2）PVT库选择器 耦合到PVT库数据库并且被配置为接收指示补充目标的选择并且通过从PVT库数据库中选择一个PVT库来响应该选择，时间签发工具稍后在PVT中的至少两个角落中使用 库对电路执行定时签入。