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公开(公告)号：US06807656B1
公开(公告)日：2004-10-19
申请号：US10407065
申请日：2003-04-03
申请人： Lihui Cao , Prasad Subbarao , David Gradin , Maad Al-Dabagh , Weidan Li
发明人： Lihui Cao , Prasad Subbarao , David Gradin , Maad Al-Dabagh , Weidan Li
IPC分类号： G06F1750
CPC分类号： G06F17/5063 , G06F17/5036
摘要： A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.
摘要翻译： 公开了一种用于在ASIC设计流程期间估计去耦电容的方法。 该方法包括对一组电网结构进行预先表征，以模拟其各自的噪声行为，并将相应的噪声行为作为噪声因子存储在表中。 在用于当前设计的ASIC设计流程中，其包括至少一个预先表征的电网结构，来自该表的相应的噪声系数用于计算当前设计的去耦电容。
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公开(公告)号：US06744081B2
公开(公告)日：2004-06-01
申请号：US10283965
申请日：2002-10-30
申请人： Radoslav Ratchkov , Maad Al-Dabagh
发明人： Radoslav Ratchkov , Maad Al-Dabagh
IPC分类号： H01L2710
CPC分类号： H01L23/5286 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit with a power and ground distribution system having a first conductive layer, a second conductive layer, and an insulating layer disposed between the first layer and the second layer. A first ring is formed in the first layer, where the first ring forms a first loop around a peripheral portion of the integrated circuit. First straps are formed in the first layer, where the first straps have connections to the first ring. First horizontal members are formed in the first layer, where the first horizontal members have connections to the first ring. Second horizontal members are formed in the first layer, where the second horizontal members do not have connections to the first ring. A second ring is formed in the second layer, where the second ring forms a second loop around the peripheral portion of the integrated circuit. The second ring is interleaved with the first ring. Second straps are formed in the second layer, where the second straps have connections to the second ring. Second vertical members are formed in the second layer, where the second vertical members have connections to the second ring. First vertical members are formed in the second layer, where the first vertical members do not have connections to the second ring. First vias form connections between the first vertical members and the first ring. Second vias form connections between the second horizontal members and the second ring. The first elements form a first subsystem such as for power, and the second elements form a second subsystem such as for ground.
摘要翻译： 一种具有电力和地面分配系统的集成电路，其具有设置在第一层和第二层之间的第一导电层，第二导电层和绝缘层。 第一环形成在第一层中，其中第一环围绕集成电路的周边部分形成第一环。 在第一层中形成第一带，其中第一带具有与第一环的连接。 第一水平构件形成在第一层中，其中第一水平构件具有到第一环的连接。 第二水平构件形成在第一层中，其中第二水平构件不具有到第一环的连接。 第二环形成在第二层中，其中第二环围绕集成电路的周边部分形成第二环。 第二环与第一环交错。 第二带形成在第二层中，其中第二带具有与第二环的连接。 第二垂直构件形成在第二层中，其中第二垂直构件具有到第二环的连接。 第一垂直构件形成在第二层中，其中第一垂直构件不具有到第二环的连接。 第一通孔在第一垂直构件和第一环之间形成连接。 第二通孔在第二水平构件和第二环之间形成连接。 第一元件形成第一子系统，例如用于电力，第二元件形成第二子系统，例如用于地面。
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公开(公告)号：US06747349B1
公开(公告)日：2004-06-08
申请号：US10335649
申请日：2002-12-31
IPC分类号： H01L2352
CPC分类号： H01L23/5286 , H01L24/06 , H01L2924/14 , H01L2924/00
摘要： A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.
摘要翻译： 用于配电网的矩形终端环放置在集成电路的上两层上，并且可以放置在某些I / O电路上。 将接合焊盘连接到终端环的捆扎带放置在集成电路的上层，最小化通孔要求并释放附加电路的空间。 此外，端接环可以适于与L形以及其它配电网一起工作。
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公开(公告)号：US20050022145A1
公开(公告)日：2005-01-27
申请号：US10924531
申请日：2004-08-23
CPC分类号： G06F17/5022 , G06F17/50
摘要： A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.
摘要翻译： 一种用于在集成电路设计中查找定时关键网络的方法和计算机程序产品包括以下步骤：（a）接收集成电路设计作为输入; （b）计算集成电路设计中每个网络的近似延迟，其中近似延迟包括串扰延迟的估计; （c）从集成电路设计中每个网络的计算延迟识别定时关键网; （d）计算每个定时关键网络的对应精确延迟; （e）用相应的精确延迟代替每个定时关键网计算的近似延迟，以产生用于集成电路设计的校正的一组净延迟; 和（f）产生用于集成电路设计的校正的一组净延迟的输出。
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公开(公告)号：US06781228B2
公开(公告)日：2004-08-24
申请号：US10339844
申请日：2003-01-10
申请人： Hiroshi Ishikawa , Thomas Antisseril , Radoslav Ratchkov , Bo Shen , Prasad Subbarao , Maad Al-Dabagh , Anwar Ali , Benjamin Mbouombouo
发明人： Hiroshi Ishikawa , Thomas Antisseril , Radoslav Ratchkov , Bo Shen , Prasad Subbarao , Maad Al-Dabagh , Anwar Ali , Benjamin Mbouombouo
IPC分类号： H01L2352
CPC分类号： H01L23/5286 , H01L24/81 , H01L2224/81801
摘要： A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.
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