利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

52 条记录 (耗时 0.034 秒)

    MANAGEMENT OF CONDITIONAL BRANCHES WITHIN A DATA PARALLEL SYSTEM
    1.
    发明申请
    MANAGEMENT OF CONDITIONAL BRANCHES WITHIN A DATA PARALLEL SYSTEM 失效
    数据并行系统中条件分支的管理

    公开(公告)号：US20120198425A1

    公开(公告)日：2012-08-02

    申请号：US13016406

    申请日：2011-01-28

    申请人： Alexandre E. Eichenberger ,  Brian Flachs ,  Dorit Nuzman ,  Ira Rosen ,  Ulrich Weigand ,  Ayal Zaks

    发明人： Alexandre E. Eichenberger ,  Brian Flachs ,  Dorit Nuzman ,  Ira Rosen ,  Ulrich Weigand ,  Ayal Zaks

    IPC分类号： G06F9/45

    CPC分类号： G06F8/456

    摘要： A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies “if-then-else” statements that offer opportunity for conditional branch conversion. The compiler converts those “if-then-else” statements into “conditional branch and prepare” statements as well as “branch return” statements. The compiler compiles source code file information containing “if-then-else” statement opportunities into compiled code, namely an executable program. The SIMD IHS employs a processor or processors to execute the executable program. During execution, the processor generates and updates SIMD lane mask information to track and manage the conditional branch loops of the executing program. The processor saves branch addresses and employs SIMD lane masks to identify conditional branch loops with different branch conditions than previous conditional branch loops. The processor may reduce SIMD IHS processing time during processing of compiled code of the original “if-then-else” statements. The processor continues processing next statements inline after all SIMD lanes are complete, while providing speculative and parallel processing capability for multiple data operations of the executable program.

    摘要翻译： 单指令多数据（SIMD）信息处理系统（IHS）的编译器标识“if-then-else”语句，为条件分支转换提供机会。 编译器将那些“if-then-else”语句转换成“条件分支和准备”语句以及“分支返回”语句。 编译器将包含“if-then-else”语句机会的源代码文件信息编译为编译代码，即可执行程序。 SIMD IHS采用处理器或处理器来执行可执行程序。 在执行期间，处理器生成并更新SIMD通道掩码信息以跟踪和管理执行程序的条件分支循环。 处理器保存分支地址，并使用SIMD通道屏蔽来识别具有不同分支条件的条件分支循环，而不是先前的条件分支循环。 在处理原始“if-then-else”语句的编译代码时，处理器可能会减少SIMD IHS处理时间。 在所有SIMD通道完成之后，处理器继续处理下一个语句，同时为可执行程序的多个数据操作提供推测性和并行处理能力。

    Management of conditional branches within a data parallel system
    2.
    发明授权
    Management of conditional branches within a data parallel system 失效
    数据并行系统中条件分支的管理

    公开(公告)号：US08726252B2

    公开(公告)日：2014-05-13

    申请号：US13016406

    申请日：2011-01-28

    申请人： Alexandre E. Eichenberger ,  Brian Flachs ,  Dorit Nuzman ,  Ira Rosen ,  Ulrich Weigand ,  Ayal Zaks

    发明人： Alexandre E. Eichenberger ,  Brian Flachs ,  Dorit Nuzman ,  Ira Rosen ,  Ulrich Weigand ,  Ayal Zaks

    IPC分类号： G06F9/45 ,  G06F15/76

    CPC分类号： G06F8/456

    摘要： A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies “if-then-else” statements that offer opportunity for conditional branch conversion. The SIMD IHS employs a processor or processors to execute the executable program. During execution, the processor generates and updates SIMD lane mask information to track and manage the conditional branch loops of the executing program. The processor saves branch addresses and employs SIMD lane masks to identify conditional branch loops with different branch conditions than previous conditional branch loops. The processor may reduce SIMD IHS processing time during processing of compiled code of the original “if-then-else” statements. The processor continues processing next statements inline after all SIMD lanes are complete, while providing speculative and parallel processing capability for multiple data operations of the executable program.

    摘要翻译： 单指令多数据（SIMD）信息处理系统（IHS）的编译器标识“if-then-else”语句，为条件分支转换提供机会。 SIMD IHS采用处理器或处理器来执行可执行程序。 在执行期间，处理器生成并更新SIMD通道掩码信息以跟踪和管理执行程序的条件分支循环。 处理器保存分支地址，并使用SIMD通道屏蔽来识别具有不同分支条件的条件分支循环，而不是先前的条件分支循环。 在处理原始“if-then-else”语句的编译代码时，处理器可能会减少SIMD IHS处理时间。 在所有SIMD通道完成之后，处理器继续处理下一个语句，同时为可执行程序的多个数据操作提供推测性和并行处理能力。

    PARALLEL LOOP MANAGEMENT
    5.
    发明申请
    PARALLEL LOOP MANAGEMENT 失效
    平行环路管理

    公开(公告)号：US20120023316A1

    公开(公告)日：2012-01-26

    申请号：US12843224

    申请日：2010-07-26

    申请人： Brian Flachs ,  Charles R. Johns ,  Ulrich Weigand

    发明人： Brian Flachs ,  Charles R. Johns ,  Ulrich Weigand

    IPC分类号： G06F9/30 ,  G06F9/32

    CPC分类号： G06F9/3887 ,  G06F8/452 ,  G06F9/30065 ,  G06F9/30076 ,  G06F9/3806 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3853 ,  G06F9/3857

    摘要： The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.

    摘要翻译： 示例性实施例包括具有用于处理具有循环的指令的处理器单元的方法，数据处理系统和计算机程序产品。 处理器单元创建具有第一组循环和第二组指令的第一组指令，其具有来自指令的第二组循环。 第一组循环与第二组循环具有不同的并行处理顺序。 处理器单元处理第一组。 处理器单元在第一组处理期间监视第一组回路中的终端。 处理器单元确定在第一组环路中正在监视的终端数量是否大于可选数量的终端。 响应于确定终端的数量大于可选择的终端数量，处理器单元停止处理第一组并处理第二组。

    Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set
    6.
    发明授权
    Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set 失效
    在可选数量的监视终端和处理第二组时，停止对第一组循环的并行处理

    公开(公告)号：US08683185B2

    公开(公告)日：2014-03-25

    申请号：US12843224

    申请日：2010-07-26

    申请人： Brian Flachs ,  Charles Ray Johns ,  Ulrich Weigand

    发明人： Brian Flachs ,  Charles Ray Johns ,  Ulrich Weigand

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3887 ,  G06F8/452 ,  G06F9/30065 ,  G06F9/30076 ,  G06F9/3806 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3853 ,  G06F9/3857

    摘要： The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.

    摘要翻译： 示例性实施例包括具有用于处理具有循环的指令的处理器单元的方法，数据处理系统和计算机程序产品。 处理器单元创建具有第一组循环和第二组指令的第一组指令，其具有来自指令的第二组循环。 第一组循环与第二组循环具有不同的并行处理顺序。 处理器单元处理第一组。 处理器单元在第一组处理期间监视第一组回路中的终端。 处理器单元确定在第一组环路中正在监视的终端数量是否大于可选数量的终端。 响应于确定终端的数量大于可选择的终端数量，处理器单元停止处理第一组并处理第二组。

    Dynamically rewriting branch instructions in response to cache line eviction
    7.
    发明授权
    Dynamically rewriting branch instructions in response to cache line eviction 有权
    动态地重写分支指令以响应缓存线驱逐

    公开(公告)号：US08782381B2

    公开(公告)日：2014-07-15

    申请号：US13444890

    申请日：2012-04-12

    申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    IPC分类号： G06F9/44

    CPC分类号： G06F8/4442 ,  G06F9/3806 ,  G06F12/0875 ,  G06F12/12

    摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

    摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

    Dynamically rewriting branch instructions to directly target an instruction cache location
    8.
    发明授权
    Dynamically rewriting branch instructions to directly target an instruction cache location 有权
    动态地重写分支指令直接指向指令高速缓存位置

    公开(公告)号：US08627051B2

    公开(公告)日：2014-01-07

    申请号：US13442919

    申请日：2012-04-10

    申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3806 ,  G06F12/0875

    摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

    摘要翻译： 提供了用于在代码的一部分中动态地重写分支指令的机制。 这些机制在代码的一部分中执行分支指令。 这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。 此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。 此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，这些机制将代码部分的执行重定向到指令高速缓存运行时系统。

    Arranging Binary Code Based on Call Graph Partitioning
    9.
    发明申请
    Arranging Binary Code Based on Call Graph Partitioning 有权
    基于调用图划分二进制代码

    公开(公告)号：US20110321021A1

    公开(公告)日：2011-12-29

    申请号：US12823244

    申请日：2010-06-25

    申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    IPC分类号： G06F9/45

    CPC分类号： G06F8/4442

    摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

    摘要翻译： 提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。 这些机制产生一部分代码的调用图。 调用图中的节点和边被加权以生成加权调用图。 然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码 调用图被组合到基于分区的各个高速缓存行。 然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

    Rewriting Branch Instructions Using Branch Stubs
    10.
    发明申请
    Rewriting Branch Instructions Using Branch Stubs 有权
    使用分支存根重写分支指令

    公开(公告)号：US20110321002A1

    公开(公告)日：2011-12-29

    申请号：US12823204

    申请日：2010-06-25

    申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

    IPC分类号： G06F9/44 ,  G06F9/45

    CPC分类号： G06F8/4436 ,  G06F8/433 ,  G06F8/4442

    摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

    摘要翻译： 提供了用于在一部分代码中重写分支指令的机制。 该机制接收一部分具有原始分支指令的源代码。 机制为原始分支指令生成分支存根。 分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。 此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。 此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。 计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预 。