公开(公告)号：US20220101887A1

公开(公告)日：2022-03-31

申请号：US17037134

申请日：2020-09-29

申请人： Alibaba Group Holding Limited

发明人： Wei HAN ,  Shuangchen LI ,  Lide DUAN ,  Hongzhong ZHENG ,  Dimin NIU ,  Yuhao WANG ,  Xiaoxin FAN

IPC分类号： G11C5/06 ,  G11C11/408 ,  G11C11/4094

摘要： The systems and methods are configured to efficiently and effectively include processing capabilities in memory. In one embodiment, a processing in memory (PIM) chip a memory array, logic components, and an interconnection network. The memory array is configured to store information. In one exemplary implementation the memory array includes storage cells and array periphery components. The logic components can be configured to process information stored in the memory array. The interconnection network is configured to communicatively couple the logic components. The interconnection network can include interconnect wires, and a portion of the interconnect wires are located in a metal layer area that is located above the memory array.

公开(公告)号：US20210311878A1

公开(公告)日：2021-10-07

申请号：US16839894

申请日：2020-04-03

申请人： Alibaba Group Holding Limited

发明人： Lide DUAN ,  Dimin NIU ,  Hongyu LIU ,  Shuangchen LI ,  Hongzhong ZHENG

IPC分类号： G06F12/0877 ,  G06F12/0831 ,  G06F12/0817 ,  G06F13/16

摘要： A cache coherency mode includes: in response to a read request from a device in the host-device system for an instance of the shared data, sending the instance of the shared data from the host device to that device; and, in response to write request from a device, storing data associated with the write request in the cache of the host device. Shared data is pinned in the cache of the host device, and is not cached in any of the other devices in the host-device system. Because there is only one cached copy of the shared data in the host-device system, the devices in that system are cache coherent.

公开(公告)号：US20240045805A1

公开(公告)日：2024-02-08

申请号：US17637783

申请日：2021-01-20

申请人： Alibaba Group Holding Limited

发明人： Lide DUAN ,  Guocai ZHU ,  Yen-kuang Chen ,  Hongzhong ZHENG

IPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0882

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0882

摘要： Core-aware caching systems and methods for non-inclusive non-exclusive shared caching based on core sharing behaviors of the data and/or instructions. In one implementation, the caching between a shared cache level and a core specific cache level can be based on physical page number (PPN) and core identifier sets for previous accesses to the respective physical page numbers. In another implementation, the caching between a shared cache level and a core specific cache level can be based on physical page number and core valid bit vector sets for previous accesses to the respective physical page numbers by each of the plurality of cores.

公开(公告)号：US20220244870A1

公开(公告)日：2022-08-04

申请号：US17166975

申请日：2021-02-03

申请人： Alibaba Group Holding Limited

发明人： Lide DUAN ,  Dimin NIU ,  Hongzhong ZHENG

IPC分类号： G06F3/06

摘要： A dynamic bias coherency configuration engine can include control logic, a host threshold register, and device threshold register and a plurality of memory region monitoring units. The memory region monitoring units can include a starting page number register, an ending page number register, a host access register and a device access register. The memory region monitoring units can be utilized by dynamic bias coherency configuration engine to configure corresponding portions of a memory space in a device bias mode or a host bias mode.

公开(公告)号：US20220058150A1

公开(公告)日：2022-02-24

申请号：US16998960

申请日：2020-08-20

申请人： Alibaba Group Holding Limited

发明人： Lide DUAN ,  Wei HAN ,  Yuhao WANG ,  Fei XUE ,  Yuanwei FANG ,  Hongzhong ZHENG

IPC分类号： G06F13/40 ,  G06N20/00 ,  G06F13/16 ,  H01L25/065 ,  H01L25/18

摘要： A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.