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公开(公告)号：US20200057707A1
公开(公告)日：2020-02-20
申请号：US15999157
申请日：2018-08-17
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Xiaowei Jiang
Abstract: The present application provides methods and systems for simulating full-system performance of a hardware device. An exemplary system for simulating full-system performance of a hardware device may include a cycle-accurate performance simulator configured to model a performance of a hardware component of a plurality of hardware components of a system, and the cycle-accurate performance simulator may include a first transactor. The system may also include a full-system simulator configured to model a performance of the plurality of hardware components of the system, and the full-system simulator includes a second transactor. The system may further include a communication mechanism between the first transactor and the second transactor, wherein the communication mechanism is configured to communicate data between the cycle-accurate performance simulator and the full-system simulator.
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公开(公告)号：US11119939B2
公开(公告)日：2021-09-14
申请号：US15682437
申请日：2017-08-21
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Xiaowei Jiang , Shu Li
IPC: G06F12/1009 , G06F12/14
Abstract: The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.
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公开(公告)号：US10761851B2
公开(公告)日：2020-09-01
申请号：US16231323
申请日：2018-12-21
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Liang Han , Xiaowei Jiang , Jian Chen
Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.
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公开(公告)号：US10733112B2
公开(公告)日：2020-08-04
申请号：US15626044
申请日：2017-06-16
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Xiaowei Jiang
IPC: G06F12/109 , G06F9/455
Abstract: An apparatus for operating an input/output (I/O) interface in a virtual machine is provided. The apparatus is configured to: map a first portion of a memory device to a configuration space of an I/O interface; obtain a first mapping table that maps a set of host space virtual addresses to a first set of physical addresses associated with the first portion of the memory device; obtain a second mapping table that maps a second set of physical addresses associated with a second portion of the memory device accessible by a virtual machine to the set of host space virtual addresses; generate a third mapping table that maps the second set of physical addresses to the first set of physical addresses; and provide the third mapping table to a device driver operating in the virtual machine, to enable the device driver to access the configuration space of the I/O interface.
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公开(公告)号：US10482024B2
公开(公告)日：2019-11-19
申请号：US15655711
申请日：2017-07-20
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Xiaowei Jiang
IPC: G06F12/00 , G06F12/0888 , G06F12/084 , G06F12/0811 , G06F12/0842 , G06F12/0846 , G06F12/1009 , G06F12/1027
Abstract: A multi-core CPU includes a Last-Level Cache (LLC) interconnected with a plurality of cores. The LLC may include a shared portion and a private portion. The shared portion may be shared by the plurality of cores. The private portion may be connected to a first core of the plurality of cores and may be exclusively assigned to the first core. The first core may be configured to initiate a data access request to access data stored in the LLC and initiate a data access request to access data stored in the LLC. The first core may route the data access request to the private portion based on the determination that the data access request is the TLS type of access request and route the data access request to the shared portion based on the determination that the data access request is not the TLS type of access request.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190050327A1
公开(公告)日：2019-02-14
申请号：US15675416
申请日：2017-08-11
Applicant: Alibaba Group Holding Limited
Inventor： Shu Li , Xiaowei Jiang
Abstract: One embodiment facilitates a write operation in a shingled magnetic recording device. During operation, the system receives, by a controller module of the device, a request to write first data, wherein the device has a plurality of bands with overlapping tracks for storing data. In response to determining that the first data is updated data corresponding to original data stored in a first band, the system appends the updated data to a second band with available storage space. The system merges the updated data with the original data.
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公开(公告)号：US10970043B2
公开(公告)日：2021-04-06
申请号：US16886613
申请日：2020-05-28
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Liang Han , Xiaowei Jiang
Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.
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公开(公告)号：US10915317B2
公开(公告)日：2021-02-09
申请号：US16215553
申请日：2018-12-10
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Liang Han , Xiaowei Jiang
Abstract: The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.
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9.发明授权公开(公告)号：US10303601B2
公开(公告)日：2019-05-28
申请号：US15675416
申请日：2017-08-11
Applicant: Alibaba Group Holding Limited
Inventor： Shu Li , Xiaowei Jiang
Abstract: One embodiment facilitates a write operation in a shingled magnetic recording device. During operation, the system receives, by a controller module of the device, a request to write first data, wherein the device has a plurality of bands with overlapping tracks for storing data. In response to determining that the first data is updated data corresponding to original data stored in a first band, the system appends the updated data to a second band with available storage space. The system merges the updated data with the original data.
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公开(公告)号：US11153289B2
公开(公告)日：2021-10-19
申请号：US15663616
申请日：2017-07-28
Applicant: ALIBABA GROUP HOLDING LIMITED
Inventor： Xiaowei Jiang
Abstract: A System-on-Chip (SoC) performs secure communication operations. The SoC may include a peripheral interface configured to communicate with a host system. The SoC may also include a network interface configured to receive network packets in a secure communication session. The SoC may further include a processor configured to execute an Operating System (OS) software and a secure communication software stack to process at least one received network packet in the secure communication session. In addition, the SoC may include a secure communication engine configured to perform cryptographic operations and generate at least one decrypted packet in the secure communication session. The at least one decrypted packet may be provided to the host system via the peripheral interface.
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