公开(公告)号：US11619914B2

公开(公告)日：2023-04-04

申请号：US17805070

申请日：2022-06-02

Applicant: Allegro MicroSystems, LLC

Inventor： Charles Myers ,  Shunming Sun ,  Adam Lee

IPC: G04F10/00 ,  H03L7/081 ,  H03L7/085 ,  G01S7/4865

Abstract: Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

公开(公告)号：US11885646B2

公开(公告)日：2024-01-30

申请号：US17400300

申请日：2021-08-12

Applicant: Allegro MicroSystems, LLC

Inventor： Charles Myers ,  Shunming Sun ,  Adam Lee

IPC: G01D18/00 ,  H01L27/146

CPC classification number: G01D18/00 ,  H01L27/14609

Abstract: Methods and apparatus for a detector system having a photodetector and an amplifier to amplify the photodetector signal. A discriminator generates an active output signal when the output from the amplifier is greater than a threshold. An injection circuit is coupled to the input of the amplifier. The injection circuit is configured to selectively inject a test pulse that mimics a pulse from the photodetector for verifying operation of the detector system.

公开(公告)号：US11585910B1

公开(公告)日：2023-02-21

申请号：US17402065

申请日：2021-08-13

Applicant: Allegro MicroSystems, LLC

Inventor： Adam Lee ,  Andrew S. Huntington ,  Charles Myers ,  Shunming Sun

IPC: G01S7/48 ,  G01S7/497 ,  G01S17/894 ,  G01S7/4863

Abstract: Methods and apparatus for nonuniformity correction (NUC) for a sensor having an avalanche photodiode (APD) array and an integrated circuit. The sensor can include anode bias control module, a passive mode module, and an active mode module. DC photocurrent from the APD array can be measured and used for controlling an anode reverse bias voltage to each element in the APD to achieve a nonuniformity correction level less than a selected threshold.

公开(公告)号：US20230051974A1

公开(公告)日：2023-02-16

申请号：US17400300

申请日：2021-08-12

Applicant: Allegro MicroSystems, LLC

Inventor： Charles Myers ,  Shunming Sun ,  Adam Lee

IPC: G01D18/00 ,  H01L27/146

Abstract: Methods and apparatus for a detector system having a photodetector and an amplifier to amplify the photodetector signal. A discriminator generates an active output signal when the output from the amplifier is greater than a threshold. An injection circuit is coupled to the input of the amplifier. The injection circuit is configured to selectively inject a test pulse that mimics a pulse from the photodetector for verifying operation of the detector system.

公开(公告)号：US20230050920A1

公开(公告)日：2023-02-16

申请号：US17402065

申请日：2021-08-13

Applicant: Allegro MicroSystems, LLC

Inventor： Adam Lee ,  Andrew S. Huntington ,  Charles Myers ,  Shunming Sun

IPC: G01S7/497 ,  G01S7/4863 ,  G01S17/894

Abstract: Methods and apparatus for nonuniformity correction (NUC) for a sensor having an avalanche photodiode (APD) array and an integrated circuit. The sensor can include anode bias control module, a passive mode module, and an active mode module. DC photocurrent from the APD array can be measured and used for controlling an anode reverse bias voltage to each element in the APD to achieve a nonuniformity correction level less than a selected threshold.

公开(公告)号：US20220390903A1

公开(公告)日：2022-12-08

申请号：US17805070

申请日：2022-06-02

Applicant: Allegro MicroSystems, LLC

Inventor： Charles Myers ,  Shunming Sun ,  Adam Lee

IPC: G04F10/00 ,  H03L7/081 ,  H03L7/085

Abstract: Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.