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    Systems and methods for performing profile-based circuit optimization using high-level system modeling
    1.
    发明授权
    Systems and methods for performing profile-based circuit optimization using high-level system modeling 有权
    使用高级系统建模执行基于简档的电路优化的系统和方法

    公开(公告)号：US09529950B1

    公开(公告)日：2016-12-27

    申请号：US14661750

    申请日：2015-03-18

    申请人： Altera Corporation

    发明人： Maryam Sadooghi-Alvandi ,  Dmitry Nikolai Denisenko ,  Andrei Mihai Hagiescu Miriste

    IPC分类号： G06F17/00 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5022 ,  G06F17/5027

    摘要： Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL. The design system may generate the optimized configuration data without performing multiple, time-consuming, HDL compilations.

    摘要翻译： 可以使用配置数据来编程集成电路以实现期望的定制逻辑电路。 可以使用逻辑设计系统来生成配置数据。 逻辑设计系统可以包括第一和第二编译器和仿真引擎。 第一编译器可以编译逻辑电路的计算机程序语言描述，以生成硬件描述语言（HDL）描述。 仿真引擎可以在加载到目标器件上时模拟逻辑电路的性能，并且可以监视仿真性能以产生表征逻辑电路的仿真性能的仿真简档数据。 第一编译器可以处理仿真的简档数据以识别在逻辑电路上执行的优化，并且可以编译优化的HDL描述。 第二个编译器可以使用优化的HDL编译优化的配置数据。 设计系统可以生成优化的配置数据，而不需要执行多个耗时的HDL编译。

    Interface circuitry for parallel computing architecture circuits
    9.
    发明授权
    Interface circuitry for parallel computing architecture circuits 有权

    公开(公告)号：US10437743B1

    公开(公告)日：2019-10-08

    申请号：US15088378

    申请日：2016-04-01

    申请人： Altera Corporation

    发明人： Davor Capalija ,  Andrei Mihai Hagiescu Miriste ,  John Stuart Freeman ,  Alan Baker

    IPC分类号： G06F13/10 ,  H04L12/935 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42

    摘要： The present embodiments relate to interface circuitry between a serial interface circuit and an array of processing elements in an integrated circuit. The interface circuitry may include a daisy chain of feeder circuits and a daisy chain of drain circuits. If desired, the interface circuitry may include multiple daisy chains of feeder circuits and/or multiple daisy chains of drain circuits. These multiple daisy chains of feeder circuits and drains circuits may be coupled in parallel, respectively. In some embodiments, the interface circuitry may include synchronization circuitry that is coupled between the daisy chains of drain circuits and the serial interface circuit. Pipeline register stages between feeder circuits and/or between drain circuits may enable the placement of the feeder circuits and/or the drain circuits spatially close to the processing elements of the array of processing elements.

    CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION
    10.
    发明申请
    CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION 审中-公开
    通道尺寸用于内部通信

    公开(公告)号：US20160378441A1

    公开(公告)日：2016-12-29

    申请号：US14749379

    申请日：2015-06-24

    申请人： Altera Corporation

    发明人： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

    IPC分类号： G06F9/45 ,  G06F9/54

    CPC分类号： G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/66

    摘要： Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

    摘要翻译： 提供了在集成电路（IC）上实现的用于动态调整内核间通信信道的大小的系统和方法。 通道，预测和内核调度不平衡的实现特性可能因素可以适当地调整用于自同步的信道，从而导致优化的稳态吞吐量。