公开(公告)号：US09442872B2

公开(公告)日：2016-09-13

申请号：US14070657

申请日：2013-11-04

申请人： Altera Corporation

发明人： Edwin Franklin Barry ,  Nikos P. Pitsianis ,  Kevin Coopman

IPC分类号： G06F15/80 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

公开(公告)号：US09009365B2

公开(公告)日：2015-04-14

申请号：US13771390

申请日：2013-02-20

申请人： Altera Corporation

发明人： Gerald George Pechanek ,  David Strube ,  Edwin Franklin Barry ,  Charles W. Kurak, Jr. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo Rodriguez ,  Marco Jacobs

IPC分类号： G06F13/36 ,  G06F15/82 ,  G06F9/30 ,  G06F13/00 ,  G06F11/263

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

公开(公告)号：US20150039856A1

公开(公告)日：2015-02-05

申请号：US14456011

申请日：2014-08-11

申请人： Altera Corporation

发明人： Nikos P. Pitsianis ,  Gerald George Pechanek ,  Ricardo Rodriguez

IPC分类号： G06F15/82 ,  G06F15/80

CPC分类号： G06F15/82 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8023 ,  G06F15/8038 ,  G06F17/142

摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

摘要翻译： 提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。 采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专用复数乘法指令和通信操作，以提供非常高的性能操作。 使用紧密封装的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。 此外，描述了用于支持组合乘法累加操作的有效技术。

公开(公告)号：US09015354B2

公开(公告)日：2015-04-21

申请号：US14456011

申请日：2014-08-11

申请人： Altera Corporation

发明人： Nikos P. Pitsianis ,  Gerald George Pechanek ,  Ricardo Rodriguez

IPC分类号： G06F9/44 ,  G06F15/82 ,  G06F15/80 ,  G06F9/30 ,  G06F17/14

CPC分类号： G06F15/82 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8023 ,  G06F15/8038 ,  G06F17/142

摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

摘要翻译： 提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。 采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专用复数乘法指令和通信操作，以提供非常高的性能操作。 使用紧密封装的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。 此外，描述了用于支持组合乘法累加操作的有效技术。