公开(公告)号：US11775268B1

公开(公告)日：2023-10-03

申请号：US17341762

申请日：2021-06-08

Applicant: Amazon Technologies, Inc.

Inventor： Preston Pengra Briggs ,  Ron Diamant ,  Robert Geva

IPC: G06F8/41 ,  G06F12/06 ,  G06F9/30

CPC classification number: G06F8/41 ,  G06F8/441 ,  G06F9/30123 ,  G06F12/0646 ,  G06F2212/1024

Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.

公开(公告)号：US11625269B1

公开(公告)日：2023-04-11

申请号：US17301343

申请日：2021-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Robert Geva ,  Taylor Goodhart ,  Ron Diamant ,  Preston Pengra Briggs

IPC: G06F9/48 ,  G06F8/41 ,  G06N3/063 ,  G06F7/24

Abstract: A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.

公开(公告)号：US11934876B1

公开(公告)日：2024-03-19

申请号：US17343435

申请日：2021-06-09

Applicant: Amazon Technologies, Inc.

Inventor： Preston Pengra Briggs

IPC: G06F9/50 ,  G06F9/30 ,  G06F12/0871

CPC classification number: G06F9/5016 ,  G06F9/30036 ,  G06F9/30101 ,  G06F12/0871

Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. A number of possible placements and a number of blocked placements in a memory of the integrated circuit device are computed for each of the set of values. At least a portion of the set of values are assigned to a set of memory locations in the memory based on the numbers of possible placements and blocked placements, resulting in a set of memory location assignments.

公开(公告)号：US11797280B1

公开(公告)日：2023-10-24

申请号：US17305150

申请日：2021-06-30

Applicant: Amazon Technologies, Inc.

Inventor： Parivallal Kannan ,  Fabio Nonato de Paula ,  Preston Pengra Briggs

IPC: G06F8/41 ,  G06F9/50 ,  G06N20/00 ,  G06N3/042

CPC classification number: G06F8/441 ,  G06F8/451 ,  G06F9/5044 ,  G06F9/5066 ,  G06N20/00 ,  G06F2209/5019 ,  G06F2212/1024 ,  G06N3/042

Abstract: Techniques to partition a neural network model for serial execution on multiple processing integrated circuit devices are described. An initial partitioning of the model into multiple partitions each corresponding to a processing integrated circuit device is performed. For each partition, an execution latency is calculated by aggregating compute clock cycles to perform computations in the partition, and weight loading clock cycles determined based on a number of weights used in the partition. The amount of data being outputted from the partition is also determined. The partitions can be adjusted by moving computations from a source partition to a target partition to change execution latencies of the partitions and the amount of data being transferred between partitions.

公开(公告)号：US12182549B1

公开(公告)日：2024-12-31

申请号：US18230988

申请日：2023-08-07

Applicant: Amazon Technologies, Inc.

Inventor： Preston Pengra Briggs ,  Ron Diamant ,  Robert Geva

IPC: G06F8/41 ,  G06F9/30 ,  G06F12/06

Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.

公开(公告)号：US12131188B1

公开(公告)日：2024-10-29

申请号：US18192081

申请日：2023-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Robert Geva ,  Taylor Goodhart ,  Ron Diamant ,  Preston Pengra Briggs

IPC: G06F9/48 ,  G06F8/41 ,  G06N3/063

CPC classification number: G06F9/4881 ,  G06F8/43 ,  G06F8/433 ,  G06N3/063

Abstract: A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.

公开(公告)号：US11144291B1

公开(公告)日：2021-10-12

申请号：US16698320

申请日：2019-11-27

Applicant: Amazon Technologies, Inc.

Inventor： Hongbin Zheng ,  Preston Pengra Briggs ,  Tobias Joseph Kastulus Edler von Koch ,  Taemin Kim ,  Randy Renfu Huang

IPC: G06F9/44 ,  G06F8/41 ,  G06N3/04

Abstract: Methods of accelerating the execution of neural networks are disclosed. A description of a neural network may be received. A plurality of operators may be identified based on the description of the neural network. A plurality of symbolic models associated with the plurality of operators may be generated. For each symbolic model, a nested loop associated with an operator may be identified, a loop order may be defined, and a set of data dependencies may be defined. A set of inter-operator dependencies may be extracted based on the description of the neural network. The plurality of symbolic models and the set of inter-operator dependencies may be analyzed to identify a combinable pair of nested loops. The combinable pair of nested loops may be combined to form a combined nested loop.