Glitch-free clock multiplexer
    1.
    发明授权

    公开(公告)号:US09612611B1

    公开(公告)日:2017-04-04

    申请号:US14869349

    申请日:2015-09-29

    CPC classification number: G06F1/08 G06F1/04 G06F1/12

    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.

    Glitch-free clock multiplexer
    2.
    发明授权

    公开(公告)号:US10198026B1

    公开(公告)日:2019-02-05

    申请号:US15475030

    申请日:2017-03-30

    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.

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