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    Glitch-free clock multiplexer
    2.
    发明授权
    Glitch-free clock multiplexer 有权

    公开(公告)号：US10198026B1

    公开(公告)日：2019-02-05

    申请号：US15475030

    申请日：2017-03-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Usama Nassir ,  Saar Gross ,  Nafea Bshara ,  Barak Wasserstrom ,  Daniel Joseph Grey

    IPC: G06F1/08 ,  G06F1/12

    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.

    Communication with components of secure environment
    4.
    发明授权
    Communication with components of secure environment 有权

    公开(公告)号：US10972449B1

    公开(公告)日：2021-04-06

    申请号：US16022271

    申请日：2018-06-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Alex Levin ,  Barak Wasserstrom ,  Georgy Zorik Machulsky ,  Saar Gross ,  Or Yochanan

    IPC: H04L29/06 ,  G06F21/44

    Abstract: Disclosed herein are techniques for enabling device communication in a secure environment. In one example, a system comprises a storage in a server, a first component in the server, the first component being isolated in a secure environment in the server, and an entry point device authorized to access the first component via the secure environment. The entry point device may receive a request to access the first component. The entry point device may store a notification in a region of the storage accessible by the first component, wherein the notification is to be read by the first component from the storage to set the first component to an operation mode. The entry point device may store operation data in the storage, wherein the operation data is to be acquired by the first component from the storage to control an operation of the first component in the operation mode.

    Storage adapter device for communicating with network storage
    5.
    发明授权
    Storage adapter device for communicating with network storage 有权

    公开(公告)号：US10162793B1

    公开(公告)日：2018-12-25

    申请号：US14869700

    申请日：2015-09-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Nafea Bshara ,  Alexander Matushevsky ,  Georgy Machulsky ,  Leah Shalev ,  Saar Gross

    IPC: H04L29/10 ,  G06F15/173 ,  H04L29/08 ,  H04L29/06 ,  G06F13/42 ,  G06F12/02

    Abstract: Provided are systems and methods for a storage adapter device for communicating with network storage. In some implementations, the storage adapter device comprises a host interface. In these implementations, the host interface may be configured to communicate with a host device using a local bus protocol. In some implementations, the storage adapter device also includes a network interface. In these implementations, the network interface may communicate with a network using a network protocol. In some implementations, the storage adapter device may be configured to communicate with a remote storage device. In some implementations, the storage adapter device may also be configured to translate a request from the host interface from the local bus protocol to the network protocol. The storage adapter device may further be configured to transmit the translated request to the remote storage device.

    Auto-detection of interconnect hangs in integrated circuits
    7.
    发明授权
    Auto-detection of interconnect hangs in integrated circuits 有权

    公开(公告)号：US11880289B2

    公开(公告)日：2024-01-23

    申请号：US17896739

    申请日：2022-08-26

    Applicant: Amazon Technologies, Inc.

    Inventor： Noga Smith ,  Ron Diamant ,  Saar Gross

    IPC: G06F11/30 ,  G06F11/14 ,  G06F13/28

    CPC classification number: G06F11/3027 ,  G06F11/1441 ,  G06F13/28

    Abstract: A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100 ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.

    Storage adapter device for communicating with network storage
    8.
    发明授权
    Storage adapter device for communicating with network storage 有权

    公开(公告)号：US11249937B1

    公开(公告)日：2022-02-15

    申请号：US16226529

    申请日：2018-12-19

    Applicant: Amazon Technologies, Inc.

    Inventor： Nafea Bshara ,  Alexander Matushevsky ,  Georgy Machulsky ,  Leah Shalev ,  Saar Gross

    IPC: G06F15/173 ,  H04L29/08 ,  G06F12/02 ,  G06F13/42 ,  H04L29/06

    Abstract: Provided are systems and methods for a storage adapter device for communicating with network storage. In some implementations, the storage adapter device comprises a host interface. In these implementations, the host interface may be configured to communicate with a host device using a local bus protocol. In some implementations, the storage adapter device also includes a network interface. In these implementations, the network interface may communicate with a network using a network protocol. In some implementations, the storage adapter device may be configured to communicate with a remote storage device. In some implementations, the storage adapter device may also be configured to translate a request from the host interface from the local bus protocol to the network protocol. The storage adapter device may further be configured to transmit the translated request to the remote storage device.

    Suspend, restart and resume to update storage virtualization at a peripheral device
    9.
    发明授权
    Suspend, restart and resume to update storage virtualization at a peripheral device 有权

    公开(公告)号：US11249647B2

    公开(公告)日：2022-02-15

    申请号：US16435372

    申请日：2019-06-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Raviprasad Venkatesha Murthy Mummidi ,  Matthew Shawn Wilson ,  Anthony Nicholas Liguori ,  Nafea Bshara ,  Saar Gross ,  Jaspal Kohli

    IPC: G06F3/06 ,  G06F12/14 ,  G06F13/20 ,  G06F13/40

    Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

    AUTO-DETECTION OF INTERCONNECT HANGS IN INTEGRATED CIRCUITS
    10.
    发明申请
    AUTO-DETECTION OF INTERCONNECT HANGS IN INTEGRATED CIRCUITS 有权

    公开(公告)号：US20220413980A1

    公开(公告)日：2022-12-29

    申请号：US17896739

    申请日：2022-08-26

    Applicant: Amazon Technologies, Inc.

    Inventor： Noga Smith ,  Ron Diamant ,  Saar Gross

    IPC: G06F11/30 ,  G06F11/14 ,  G06F13/28

    Abstract: A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.

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