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    Configurable address decoder
    1.
    发明授权
    Configurable address decoder 有权

    公开(公告)号：US12236260B1

    公开(公告)日：2025-02-25

    申请号：US17643572

    申请日：2021-12-09

    Applicant: Amazon Technologies, Inc.

    Inventor： Dan Saad ,  Guy Nakibly ,  Lev Vaskevich ,  Aviv Bonomo

    IPC: G06F9/46 ,  G06F9/54

    Abstract: An address decoder for a system is disclosed that can be used for different source nodes in the system. Each address decoder can be configured to perform a plurality of decode methods that can be customized for each source node. A first decode method can be used to determine a target node from a plurality of target nodes based on a destination address of the transaction. A second decode method can be used to assign a dedicated target node as the target node irrespective of the destination address of the transaction. The second decode method can be used to route the transaction to the dedicated target node for testing and verification operations.

    Transaction ordering management
    3.
    发明授权
    Transaction ordering management 有权

    公开(公告)号：US11748285B1

    公开(公告)日：2023-09-05

    申请号：US16452233

    申请日：2019-06-25

    Applicant: Amazon Technologies, Inc.

    Inventor： Roi Ben Haim ,  Guy Nakibly ,  Adi Habusha ,  Simaan Bahouth

    IPC: G06F13/38 ,  G06F9/455 ,  G11C7/10 ,  H04L69/22

    CPC classification number: G06F13/387 ,  G06F9/45533 ,  G11C7/1006 ,  H04L69/22 ,  G06F2213/0026

    Abstract: Ordering rules, such as those enforced by the peripheral component interconnect express (PCIe) protocol for data communications, can be intelligently enforced for independent transactions. A single device might host or be associated with multiple PCIe devices, such as virtual machines, and treating requests from these separate PCIe devices as coming from separate domains enables the ordering rules to be bypassed for certain transactions. Further, since a virtual machine might host multiple applications or be associated with multiple processors that can submit independent requests, the ordering rules can be bypassed at the transaction level in at least some instances. The ability to intelligently bypass ordering rules can help to improve the performance of the overall system, as requests do not need to be unnecessarily delayed and data storage capacity can be more fully utilized.

    Flexible remote direct memory access
    6.
    发明授权
    Flexible remote direct memory access 有权

    公开(公告)号：US10509764B1

    公开(公告)日：2019-12-17

    申请号：US15164601

    申请日：2016-05-25

    Applicant: Amazon Technologies, Inc.

    Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

    IPC: G06F15/167 ,  H04L29/06 ,  G06F16/22

    Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

    Glitch-free clock multiplexer
    7.
    发明授权
    Glitch-free clock multiplexer 有权

    公开(公告)号：US09612611B1

    公开(公告)日：2017-04-04

    申请号：US14869349

    申请日：2015-09-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Usama Nassir ,  Saar Gross ,  Nafea Bshara ,  Barak Wasserstrom ,  Daniel Joseph Grey

    IPC: G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/12

    Abstract: In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.

    Non-coherent and coherent connections in a multi-chip system
    9.
    发明授权
    Non-coherent and coherent connections in a multi-chip system 有权

    公开(公告)号：US11880327B1

    公开(公告)日：2024-01-23

    申请号：US17643132

    申请日：2021-12-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Barak Wasserstrom ,  Yaniv Shapira ,  Erez Izenberg ,  Adi Habusha

    IPC: G06F13/40

    CPC classification number: G06F13/4027

    Abstract: A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

    EMULATED ENDPOINT CONFIGURATION
    10.
    发明申请
    EMULATED ENDPOINT CONFIGURATION 有权

    公开(公告)号：US20220253392A1

    公开(公告)日：2022-08-11

    申请号：US17660797

    申请日：2022-04-26

    Applicant: Amazon Technologies, Inc.

    Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Georgy Machulsky

    IPC: G06F13/10 ,  G06F13/24 ,  G06F13/42 ,  G06F9/50

    Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

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