公开(公告)号：US09235673B2

公开(公告)日：2016-01-12

申请号：US14288531

申请日：2014-05-28

申请人： Amir Grinshpon ,  Osnat Arad ,  Asher Berkovitz

发明人： Amir Grinshpon ,  Osnat Arad ,  Asher Berkovitz

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/84

摘要： An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.

摘要翻译： 提供了集成电路设计，计算机程序产品和非暂时有形计算机可读存储介质的分层集成电路设计的设备和方法。 该装置包括用于接收分层集成电路设计的输入，用于选择候选输出引脚的选择器，用于调整分级集成电路设计的克隆器，用于调整分级集成电路设计的重新连接器以及用于输出分级集成电路设计的输出 适应分层电路设计。 可选地，该装置包括定时改进剂。 该装置选择作为具有矛盾的定时违规的至少两个定时路径上的节点的IP块的候选输出引脚。 克隆候选输出引脚，并且至少一个定时路径连接到IP块的一个实例的克隆输出引脚。

公开(公告)号：US09542523B2

公开(公告)日：2017-01-10

申请号：US14424220

申请日：2012-09-14

申请人： Michael Priel ,  Asher Berkovitz ,  Slavaf Fleshel ,  Amir Grinshpon ,  Dan Kuzmin ,  Yoav Miller

发明人： Michael Priel ,  Asher Berkovitz ,  Slavaf Fleshel ,  Amir Grinshpon ,  Dan Kuzmin ,  Yoav Miller

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031

摘要： A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.

摘要翻译： 描述了用于在集成电路（IC）设计中选择用于克隆的数据路径元素的方法和装置。 该方法包括对IC设计中的至少一个数据路径执行定时分析以确定至少一个数据路径的至少一个定时松弛值，计算至少一个注释的延迟值，以克隆至少一个数据中的候选元素 路径，根据至少一个计算出的注释延迟值计算至少一个数据路径的至少一个经修改的松弛值，以及至少部分地基于至少一个修改的松弛值来验证候选元素的克隆。

公开(公告)号：US20150199468A1

公开(公告)日：2015-07-16

申请号：US14424220

申请日：2012-09-14

申请人： Michael Priel ,  Asher Berkovitz ,  Slavaf Fleshel ,  Amir Grinshpon ,  Dan Kuzmin ,  Yoav Miller

发明人： Michael Priel ,  Asher Berkovitz ,  Slavaf Fleshel ,  Amir Grinshpon ,  Dan Kuzmin ,  Yoav Miller

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031

摘要： A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.

摘要翻译： 描述了用于在集成电路（IC）设计中选择用于克隆的数据路径元素的方法和装置。 该方法包括对IC设计中的至少一个数据路径执行定时分析以确定至少一个数据路径的至少一个定时松弛值，计算至少一个注释的延迟值，以克隆至少一个数据中的候选元素 路径，根据至少一个计算出的注释延迟值计算至少一个数据路径的至少一个经修改的松弛值，以及至少部分地基于至少一个修改的松弛值来验证候选元素的克隆。

公开(公告)号：US07251797B2

公开(公告)日：2007-07-31

申请号：US10994858

申请日：2004-11-22

申请人： Murat R. Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran V. Panda ,  Vladimir P. Zolotov

发明人： Murat R. Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran V. Panda ,  Vladimir P. Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

摘要翻译： 用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。 有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何 部分316对受害者时机的影响超出受害者定时窗口。 有效的延迟时间用于调整受害者计时窗口。 基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u 1）（613,625）。

公开(公告)号：US20060112359A1

公开(公告)日：2006-05-25

申请号：US10994858

申请日：2004-11-22

申请人： Murat Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran Panda ,  Vladimir Zolotov

发明人： Murat Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran Panda ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

摘要翻译： 用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。 有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何 部分316对受害者时机的影响超出受害者定时窗口。 有效的延迟时间用于调整受害者计时窗口。 基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u1）（613,625）。