-
公开(公告)号：US08181129B2
公开(公告)日：2012-05-15
申请号：US12249320
申请日：2008-10-10
申请人： Amit Gupta , Charles W. Selvidge
发明人： Amit Gupta , Charles W. Selvidge
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5059
摘要： Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops.
摘要翻译： 本发明的方面涉及将非振荡组合环转换为非循环电路。 组合环可以被建模为状态保持元件，其中使用边缘敏感锁存器来断开非振荡环路。 除了提供一种初始仅由门组成的组合循环（即，最初不包括任何状态保持元件）的方式之外，还可以转换具有通过用户锁存器的路径的循环。 所提出的方法可以与小循环和大循环一起使用。
-
公开(公告)号：US20090044157A1
公开(公告)日：2009-02-12
申请号：US12249320
申请日：2008-10-10
申请人： Amit Gupta , Charles W. Selvidge
发明人： Amit Gupta , Charles W. Selvidge
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5059
摘要： Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops.
摘要翻译： 本发明的方面涉及将非振荡组合环转换为非循环电路。 组合环可以被建模为状态保持元件，其中使用边缘敏感锁存器来断开非振荡环路。 除了提供一种初始仅由门组成的组合循环（即，最初不包括任何状态保持元件）的方式之外，还可以转换具有通过用户锁存器的路径的循环。 所提出的方法可以与小循环和大循环一起使用。
-
公开(公告)号：US07454722B2
公开(公告)日：2008-11-18
申请号：US11068036
申请日：2005-03-01
申请人： Amit Gupta , Charles W. Selvidge
发明人： Amit Gupta , Charles W. Selvidge
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5059
摘要： Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops.
摘要翻译： 本发明的方面涉及将非振荡组合环转换为非循环电路。 组合环可以被建模为状态保持元件，其中使用边缘敏感锁存器来断开非振荡环路。 除了提供一种初始仅由门组成的组合循环（即，最初不包括任何状态保持元件）的方式之外，还可以转换具有通过用户锁存器的路径的循环。 所提出的方法可以与小循环和大循环一起使用。
-
公开(公告)号：US08516411B2
公开(公告)日：2013-08-20
申请号：US13017929
申请日：2011-01-31
CPC分类号： G06F17/505 , G06F17/5027
摘要： Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the circuit design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” the first description of the circuit design into a third description for the circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the circuit design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of a corresponding portion of the circuit design.
摘要翻译： 提供了用于选择编译参数值的技术和工具，用于将诸如寄存器传送语言描述的电路设计的第一描述编译成电路设计的第二描述，诸如用于用仿真器实现的模型描述。 根据本发明的各种示例，编译工具将电路设计的第一描述“详细说明”为电路设计的第三描述。 通常，第三描述或“阐述”将跨越在电路设计的第一描述中表示的一个或多个分层边界，使得该阐述将表示第一描述设计中的两个或多个分级模块的至少一部分，根据 非等级或“平”的方式。 而且，利用本发明的一些实施方案，该阐述可以仅包括电路设计的对应部分的简单表示。
-
公开(公告)号：US06961691B1
公开(公告)日：2005-11-01
申请号：US09539463
申请日：2000-03-30
CPC分类号： G06F17/5027
摘要： A method allows two substantially asynchronous system components of a logic emulation system to exchange data packets with reference to a clock signal of predetermined frequency. In one example, each bit is transmitted across the system components over two or more cycles of the clock signal. The reference clock signal can be distributed to the two system components from a common clock signal generator, or can be generated locally independently.
摘要翻译： 一种方法允许逻辑仿真系统的两个基本上异步的系统组件参考预定频率的时钟信号来交换数据分组。 在一个示例中，每个位在时钟信号的两个或多个周期上跨系统组件传输。 参考时钟信号可以从公共时钟信号发生器分配给两个系统组件，或者可以在本地独立生成。
-
公开(公告)号：US6039771A
公开(公告)日：2000-03-21
申请号：US65237
申请日：1998-04-23
IPC分类号： C10L1/08
CPC分类号： C10L1/08
摘要： An energy fortified diesel fuel is provided containing a hydrocarbon additive wherein greater than 50% vaporizes at or above about 650.degree. F. and diesel fuel of which about 90% of the diesel fuel vaporizes at or below about 640.degree. F. or about 95% of the diesel fuel vaporizes at or below about 698.degree. F. This energy fortified diesel fuel is made by distilling a heavy hydrocarbon fraction such as slurry oil or heavy cycle oil obtained from an FCC unit or a heavy hydrocarbon fraction obtained from a steam cracker unit at a temperature of between about 500 and 750.degree. F. and at a pressure of between about 1 mm Hg and 10 psig to remove contaminants, removing distillate from this distillation, and mixing the distillate with diesel fuel, wherein about 90% of the diesel fuel vaporizes at or below about 640.degree. F. or about 95% of the diesel fuel vaporizes at or below about 698.degree. F., to form an energy fortified diesel fuel. This energy fortified diesel fuel is a desirable fuel for off highway heavy duty and "very" heavy duty compression ignition engines.
摘要翻译： 提供了一种能量强化的柴油燃料，其含有烃添加剂，其中大于50％在大约650°F或更高的温度下蒸发，其中约90％的柴油燃料在等于或低于约640°F或大约95％ 的柴油燃料在等于或低于约698°F下蒸发。该能量强化柴油燃料是通过蒸馏重质烃馏分，例如从FCC单元获得的淤浆油或重质循环油或从蒸汽裂化装置获得的重质烃馏分 在约500-750°F的温度和约1mmHg至10psig之间的压力下去除污染物，从该蒸馏中除去馏出物，并将馏出物与柴油混合，其中约90％的柴油 燃料在大约640°F或以下蒸发，或大约95％的柴油燃料在等于或低于约698°F下蒸发，以形成能量强化的柴油燃料。 这种能量强化的柴油燃料是公路重型和“非常”重型压缩点火发动机的理想燃料。
-
公开(公告)号：US07480610B2
公开(公告)日：2009-01-20
申请号：US11181036
申请日：2005-07-12
IPC分类号： G06F9/455
CPC分类号： G06F17/5027 , G06F11/3636 , G06F11/3692
摘要： A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.
摘要翻译： 用于仿真系统的工具，可以获得电路设计的独立分区的状态值。 当仿真分区时，仿真系统在每个时钟周期获取指定分区的输入值，并以间隔获取指定分区的状态值。 使用指定电路设计分区的软件模型的状态和输入值，该工具将在每个时钟周期计算分区的状态值。 软件模型可以对应于用于跨多个可配置逻辑元件设备（例如FPGA）实现电路设计的分区信息。 因此，每个软件模型可以对应于在离散FPGA集成电路上仿真的电路设计的部分。
-
8.发明授权Functional verification of logic and memory circuits with multiple asynchronous domains 有权具有多个异步域的逻辑和存储器电路的功能验证公开(公告)号：US07143377B1
公开(公告)日：2006-11-28
申请号：US10701598
申请日：2003-11-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： In an emulation system, a method is provided to schedule evaluations of state elements and memory elements receiving signals from multiple asynchronous clock domains, such that causality and hold time requirements are satisfied. In addition, a method is provided such that logic signals responsive to multiple asynchronous clock domains are transported along separate single domain path of substantially equal transit times. In one implementation, the scheduling method computes departure times and ready times for output and input terminals of logic modules, such as FPGAS.
摘要翻译： 在仿真系统中，提供了一种方法来调度对来自多个异步时钟域的信号的状态元素和存储元件的评估，从而满足因果关系和保持时间要求。 此外，提供了一种方法，使得响应于多个异步时钟域的逻辑信号沿着基本相等的传送时间的单独的单个域路径被传送。 在一个实现中，调度方法计算诸如FPGAS的逻辑模块的输出和输入端的出发时间和就绪时间。
-
9.发明授权Functional verification of logic and memory circuits with multiple asynchronous domains 有权具有多个异步域的逻辑和存储器电路的功能验证公开(公告)号：US06817001B1
公开(公告)日：2004-11-09
申请号：US10103617
申请日：2002-03-20
IPC分类号： G06F1750
CPC分类号： G06F17/5027
摘要： In an emulation system, a method is provided to schedule evaluations of state elements and memory elements receiving signals from multiple asynchronous clock domains, such that causality and hold time requirements are satisfied. In addition, a method is provided such that logic signals responsive to multiple asynchronous clock domains are transported along separate single domain path of substantially equal transit times. In one implementation, the scheduling method computes departure times and ready times for output and input terminals of logic modules, such as FPGAs.
-
10.发明授权Transition analysis and circuit resynthesis method and device for digital circuit modeling 失效数字电路建模的转换分析与电路再合成方法及装置
公开(公告)号：US6009531A
公开(公告)日：1999-12-28
申请号：US863963
申请日：1997-05-27
CPC分类号： G06F17/5027 , G06F1/04 , G06F1/10 , G06F17/5054
摘要： A method of configuring a configurable logic system, including a single or multi-FPGA network, is disclosed in which an internal clock signal is defined that has a higher frequency than timing signals the system receives from the environment in which it is operating. The frequency can be at least ten times higher than a frequency of the environmental timing signals. The logic system is configured to have a controller that coordinates operation of its logic operation in response to the internal clock signal and environmental timing signals. Specifically, the controller is a finite state machine that provides control signals to sequential logic elements such as flip-flops. The logic elements are clocked by the internal clock signal. In the past, emulation or simulation devices, for example, operated in response to timing signals from the environment. A new internal clock signal, invisible to the environment, rather than the timing signals is used to control the internal operations of the devices. Additionally, a specific set of transformations are disclosed that enable the conversion of a digital circuit design with an arbitrary clocking methodology into a single clock synchronous circuit.
摘要翻译： 公开了一种配置包括单FPGA或多FPGA网络的可配置逻辑系统的方法，其中定义了内部时钟信号，该内部时钟信号的频率高于系统从其正在运行的环境接收的定时信号。 频率可以比环境定时信号的频率高至少十倍。 逻辑系统被配置为具有响应于内部时钟信号和环境定时信号来协调其逻辑操作的操作的控制器。 具体来说，控制器是向诸如触发器的顺序逻辑元件提供控制信号的有限状态机。 逻辑元件由内部时钟信号计时。 在过去，例如，仿真或仿真设备响应于来自环境的定时信号而操作。 用于环境不可见的新内部时钟信号而不是定时信号用于控制设备的内部操作。 此外，公开了一种特定的变换集合，其能够将具有任意时钟方法的数字电路设计转换为单个时钟同步电路。
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.029 秒)
