公开(公告)号：US20180338063A1

公开(公告)日：2018-11-22

申请号：US15685379

申请日：2017-08-24

Applicant: Analog Devices Global

Inventor： David O'Neill ,  Amogh D. Thaly ,  David Rowe ,  Niall D. O'Connell ,  Lucas Valentin Garcia

IPC: H04N1/333 ,  H04N1/327

CPC classification number: H04N1/33346 ,  H04N1/32702 ,  H04N1/33323 ,  H04N1/33361 ,  H04N21/43635

Abstract: This disclosure relates generally to communicating video content and other data over networks. An example apparatus includes a transmitter for communicating data via a serial link with a receiver. The transmitter includes an input, an output interface to the serial link, and translation circuitry. The input includes multiple input data lanes and a clock lane, and the input is configured to concurrently receive data on the multiple input data lanes aligned with a clock signal received on the clock lane according to a multi-lane communication protocol. The output interface is a clock-less interface and includes a number of output data lanes less than a number of the multiple input data lanes. The translation circuitry translates the data received according to the multi-lane communication protocol to a serial link communication protocol for transmission on the serial link.

公开(公告)号：US10594892B2

公开(公告)日：2020-03-17

申请号：US15685379

申请日：2017-08-24

Applicant: Analog Devices Global

Inventor： David O'Neill ,  Amogh D. Thaly ,  David Rowe ,  Niall D. O'Connell ,  Lucas Valentin Garcia

IPC: H04N1/333 ,  H04N21/4363 ,  H04N1/327

Abstract: This disclosure relates generally to communicating video content and other data over networks. An example apparatus includes a transmitter for communicating data via a serial link with a receiver. The transmitter includes an input, an output interface to the serial link, and translation circuitry. The input includes multiple input data lanes and a clock lane, and the input is configured to concurrently receive data on the multiple input data lanes aligned with a clock signal received on the clock lane according to a multi-lane communication protocol. The output interface is a clock-less interface and includes a number of output data lanes less than a number of the multiple input data lanes. The translation circuitry translates the data received according to the multi-lane communication protocol to a serial link communication protocol for transmission on the serial link.