公开(公告)号：US20170012631A1

公开(公告)日：2017-01-12

申请号：US14794661

申请日：2015-07-08

Applicant: Analog Devices Global

Inventor： Pablo Cruz Dato ,  Declan D. Dalton ,  Patrick G. Crowley

IPC: H03L7/099 ,  H03L7/081

Abstract: A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.

Abstract translation: 一种包括多频带振荡器的锁相环（PLL）和被配置为存储振荡器的控制输入的存储器。 PLL可在校准模式中操作，其中PLL被配置为响应于振荡器的第一频带上的第一控制输入阈值而获取对应于由振荡器产生的频率的PLL的频率受控字（FCW）; 在与所述第一频带相邻的所述振荡器的第二频带上产生对应于所述FCW的频率; 识别第二控制输入，使振荡器产生对应于所述FCW的所述频率，并将所述第二控制输入存储在存储器中。