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公开(公告)号：US10295580B2
公开(公告)日：2019-05-21
申请号：US15284374
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Pablo Cruz Dato , Declan M. Dalton
Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
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公开(公告)号：US20180097522A1
公开(公告)日：2018-04-05
申请号：US15284190
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
CPC classification number: H03L7/093 , H03K3/80 , H03K4/90 , H03L7/0991 , H03L7/104 , H03L7/107 , H03L7/12 , H03L2207/06
Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
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公开(公告)号：US10340926B2
公开(公告)日：2019-07-02
申请号：US15284190
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
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公开(公告)号：US10931290B2
公开(公告)日：2021-02-23
申请号：US15942119
申请日：2018-03-30
Applicant: Analog Devices Global Unlimited Company
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
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Patent Agency Ranking
公开(公告)号：US20180095119A1
公开(公告)日：2018-04-05
申请号：US15284374
申请日：2016-10-03
Applicant: Analog Devices Global
Inventor： Vamshi Krishna Chillara , Pablo Cruz Dato , Declan M. Dalton
CPC classification number: G01R23/02 , H03L7/08 , H03L7/091 , H03L7/0993 , H03L7/1075 , H03L2207/50
Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
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公开(公告)号：US10727848B2
公开(公告)日：2020-07-28
申请号：US14794661
申请日：2015-07-08
Applicant: Analog Devices Global
Inventor： Pablo Cruz Dato , Declan M. Dalton , Patrick G. Crowley
Abstract: A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.
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公开(公告)号：US10509104B1
公开(公告)日：2019-12-17
申请号：US16102113
申请日：2018-08-13
Applicant: Analog Devices Global Unlimited Company
Inventor： Pablo Cruz Dato
Abstract: Apparatus and methods for synchronization of multiple semiconductor dies are provided herein. In certain implementations, a reference clock signal is distributed to two or more semiconductor dies that each include at least one data converter. The two or more dies include a master die that generates a data converter synchronization signal, and at least one slave die that processes the data converter synchronization signal to align timing of data conversion operations across the dies, for instance, to obtain a high degree of timing coherence for digital sampling. In certain implementations, the dies correspond to radar chips of a radar system, and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. Additionally, the master radar chip generates a ramp synchronization signal to synchronize transmission sequencing across the radar chips and/or to provide phase alignment of ADC clock signals.
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公开(公告)号：US20190305785A1
公开(公告)日：2019-10-03
申请号：US15942119
申请日：2018-03-30
Applicant: Analog Devices Global Unlimited Company
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
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9.发明申请PHASE-LOCKED LOOP HAVING A MULTI-BAND OSCILLATOR AND METHOD FOR CALIBRATING SAME 审中-公开具有多带振荡器的锁相环及其校准方法公开(公告)号：US20170012631A1
公开(公告)日：2017-01-12
申请号：US14794661
申请日：2015-07-08
Applicant: Analog Devices Global
Inventor： Pablo Cruz Dato , Declan D. Dalton , Patrick G. Crowley
Abstract: A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.
Abstract translation: 一种包括多频带振荡器的锁相环（PLL）和被配置为存储振荡器的控制输入的存储器。 PLL可在校准模式中操作，其中PLL被配置为响应于振荡器的第一频带上的第一控制输入阈值而获取对应于由振荡器产生的频率的PLL的频率受控字（FCW）; 在与所述第一频带相邻的所述振荡器的第二频带上产生对应于所述FCW的频率; 识别第二控制输入，使振荡器产生对应于所述FCW的所述频率，并将所述第二控制输入存储在存储器中。
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