公开(公告)号：US20180183436A1

公开(公告)日：2018-06-28

申请号：US15388726

申请日：2016-12-22

Applicant: Analog Devices Global

Inventor： Roderick McLachlan ,  Fergus Downey

IPC: H03K17/687

CPC classification number: H03K17/6872 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/5018

Abstract: Described are various techniques that can minimize the use of high-voltage devices in a unity-gain buffer that can be used in a high voltage application, while providing a circuit that generates an output that is an accurately buffered version of the input.

公开(公告)号：US10200055B2

公开(公告)日：2019-02-05

申请号：US15863313

申请日：2018-01-05

Applicant: Analog Devices Global

Inventor： Peter Enright ,  Martina Mincica ,  Fergus Downey

IPC: H03M1/66 ,  H03M1/08 ,  H03M1/10

Abstract: Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.