公开(公告)号：US20170133041A1

公开(公告)日：2017-05-11

申请号：US15321743

申请日：2015-07-07

Applicant: Analog Devices Global

Inventor： Mikael M. MORTENSEN ,  Kim Spetzler BERTHELSEN ,  Robert ADAMS ,  Cyrill A. MARTIN ,  Andrew MILIA ,  Eric G. NESTLER

IPC: G10L25/78 ,  G10L25/18 ,  G10L15/02 ,  G10L25/15

CPC classification number: G10L25/78 ,  G10L15/02 ,  G10L25/15 ,  G10L25/18 ,  G10L25/81 ,  G10L25/84

Abstract: Many processes for audio signal processing can benefit from voice activity detection, which aims to detect the presence of speech as opposed to silence or noise. The present disclosure describes, among other things, leveraging energy-based features of voice and insights on first and second formant frequencies of vowels to provide a low-complexity and low-power voice activity detector. A pair of two channels is provided whereby each channel is configured to detect voice activity in respective frequency bands of interest. Simultaneous activity detected in both channels can be a sufficient condition for determining that voice is present. More channels or pairs of channels can be used to detect different types of voices to improve detection and/or to detect voices present in different audio streams.

公开(公告)号：US20210194497A1

公开(公告)日：2021-06-24

申请号：US16074356

申请日：2017-02-01

Applicant: Analog Devices Global Unlimited Company

Inventor： David LAMB ,  Mayur ANVEKAR ,  Robert ADAMS

IPC: H03M3/00 ,  H03H17/02 ,  H03H17/06

Abstract: A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to quantize an analog input signal at an oversampled rate, and output an sigma delta modulated signal, a transposed polynomial decimator circuit to decimate the sigma delta modulated signal, and output a first decimated signal, and an integer decimator circuit to decimate the first decimated signal by an integer factor and output a second decimated signal having a desired output data rate. The transposed polynomial decimator circuit has a transposed polynomial filter circuit and a digital phase locked loop circuit, which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate, and outputs an intersample position parameter to the transposed polynomial filter circuit.