公开(公告)号：US10171102B1

公开(公告)日：2019-01-01

申请号：US15865742

申请日：2018-01-09

Applicant: Analog Devices Global Unlimited Company

Inventor： Hajime Shibata ,  Yunzhi Dong ,  Zhao Li ,  Trevor Clifford Caldwell ,  Wenhua William Yang

IPC: H03M1/12 ,  H03M3/00 ,  H03M1/66 ,  H03M1/06

Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.