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公开(公告)号：US10171102B1
公开(公告)日：2019-01-01
申请号：US15865742
申请日：2018-01-09
Applicant: Analog Devices Global Unlimited Company
Inventor： Hajime Shibata , Yunzhi Dong , Zhao Li , Trevor Clifford Caldwell , Wenhua William Yang
Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.
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公开(公告)号：US10181860B1
公开(公告)日：2019-01-15
申请号：US15794367
申请日：2017-10-26
Applicant: Analog Devices Global Unlimited Company
Inventor： Sharvil Pradeep Patil , Hajime Shibata , Wenhua William Yang , David Nelson Alldred , Yunzhi Dong , Gabriele Manganaro , Kimo Tam
Abstract: A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.
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