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    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
    2.
    发明申请
    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
    通过/ BSM模式优化，可以降低单个和多个芯片模块上的直流梯度和引脚电流密度

    公开(公告)号：US20070022398A1

    公开(公告)日：2007-01-25

    申请号：US11184350

    申请日：2005-07-19

    申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    IPC分类号： G06F17/50 ,  H01L21/00

    CPC分类号： H01L23/49833 ,  G06F17/5068 ,  H01L23/50 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

    摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

    摘要翻译： 通过将两个不同的电压域分配给载体的接触表面的两个分开的区域，同时为两个电压域提供公共电接地来设计诸如集成电路芯片的电子装置的载体。 集成电路芯片可以是具有额定工作电压的微处理器，并且两个电压域的不同电压都在标称工作电压的公差范围内，但是一个电压域与高功率密度区域 微处理器（例如，微处理器内核）并提供略高的电压。 较高的电源电压域优选地具有大于1的电压引脚与接地引脚的比率。