公开(公告)号：US5471428A

公开(公告)日：1995-11-28

申请号：US159181

申请日：1993-11-30

申请人： Andrea Baroni ,  Giovanni Mastrodomenico ,  Taliercio Michele ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

发明人： Andrea Baroni ,  Giovanni Mastrodomenico ,  Taliercio Michele ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

IPC分类号： G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/14

摘要： A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure. The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

摘要翻译： 单端口RAM生成器架构，用于在CAD环境中生成不同的RAM结构，并测试不同RAM结构的操作能力。 该架构包括静态RAM矩阵和自定时架构，其包括控制逻辑，虚拟行和虚拟列，分别具有字线和所述矩阵的位列的等效负载。 虚拟列以比相应位列更快的速率放电，优化定时并降低功耗。 不同的列复用器选择为选定的RAM大小提供不同的RAM，每个RAM具有略微不同的硅面积和时序性能。

公开(公告)号：US5703821A

公开(公告)日：1997-12-30

申请号：US562736

申请日：1995-11-27

申请人： Andrea Baroni ,  Giovanni Mastrodomenico ,  Michele Taliercio ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

发明人： Andrea Baroni ,  Giovanni Mastrodomenico ,  Michele Taliercio ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

IPC分类号： G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/14

摘要： A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

摘要翻译： 单端口RAM生成器架构，用于在CAD环境中生成不同的RAM结构，并测试不同RAM结构的操作能力。该架构包括一个静态RAM矩阵和一个自定时架构，其中包括一个控制逻辑 ，具有分别具有所述矩阵的字线和位列的等效负载的虚拟行和虚拟列。 虚拟列以比相应位列更快的速率放电，优化定时并降低功耗。 不同的列复用器选择为选定的RAM大小提供不同的RAM，每个RAM具有略微不同的硅面积和时序性能。