公开(公告)号：US06598190B1

公开(公告)日：2003-07-22

申请号：US09175220

申请日：1998-10-19

申请人： Piero Capocelli ,  Michele Taliercio ,  Rajamohan Varambally ,  Andrea Baroni

发明人： Piero Capocelli ,  Michele Taliercio ,  Rajamohan Varambally ,  Andrea Baroni

IPC分类号： G11C2900

CPC分类号： G11C29/72

摘要： A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs. The memory element selection circuit generation algorithm having a subroutine for generating a variable-size content-addressable memory representation having a plurality of content-addressable memory locations each one associated to a respective memory element or to a redundant memory element, each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value.

摘要翻译： 一种用于在CAD环境中生成存储器件的存储器件发生器，所述发生器由包含预定义的基本电路部件的库文件组成; 存储器阵列生成算法与库文件交互以产生具有可变数量的存储器元件的可变大小的存储器阵列表示，以及至少一个冗余存储器元件; 存储器元件选择电路生成算法与库文件交互，用于产生与存储器阵列相关联的存储器元件选择电路，用于根据存储器设备地址输入选择至少一个存储器元件。 存储元件选择电路生成算法具有用于生成具有多个可内容寻址的存储器位置的可变大小内容可寻址存储器表示的子程序，每个内容寻址存储器位置各自与相应的存储器元件或冗余存储器元件相关联， 可寻址存储器位置适于存储存储器件地址输入的一组值中的一个，并且当存储器件地址输入采用一个值时用于选择相应的存储器元件或冗余存储器元件。

公开(公告)号：US06061286A

公开(公告)日：2000-05-09

申请号：US53720

申请日：1998-04-01

申请人： Andrea Baroni ,  Danilo Rimondi ,  Michele Taliercio ,  Cosimo Torelli

发明人： Andrea Baroni ,  Danilo Rimondi ,  Michele Taliercio ,  Cosimo Torelli

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C11/419

摘要： A memory device comprises an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state.

摘要翻译： 存储器件包括以行和列布置的存储器单元的阵列，用于将行解码器的相应选择输出发送到各行的多个门，与存储器单元基本相同的虚拟存储器单元的虚拟列，用于预充电的预充电装置 当没有行被选择时处于预充电电位的列和虚拟列，以及用于在各个编程电位设置所选择的列的编程装置。 该装置包括虚拟存储单元预设装置，用于当没有行被选择时，以第一逻辑状态预设虚拟存储单元;虚拟列编程装置，用于将虚拟列设置在与第一逻辑相反的第二逻辑状态的规定编程电位 状态和第一检测器装置，用于检测虚拟列已经从预充电电位放电到规定的编程电位，并因此使能所述多个门。 每个门具有耦合到相应的虚拟存储器单元的输入，使得一旦各个空存储器单元从第一逻辑状态切换到第二逻辑状态，门被禁止。

公开(公告)号：US4875020A

公开(公告)日：1989-10-17

申请号：US287299

申请日：1988-12-21

申请人： Vincenzo Daniele ,  Marco M. Monti ,  Michele Taliercio ,  Piero Capocelli

发明人： Vincenzo Daniele ,  Marco M. Monti ,  Michele Taliercio ,  Piero Capocelli

IPC分类号： H01L27/04 ,  G06J1/00 ,  H01L21/82 ,  H01L21/822 ,  H03G3/02 ,  H03G5/02

CPC分类号： G06J1/00

摘要： An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.

公开(公告)号：US5703821A

公开(公告)日：1997-12-30

申请号：US562736

申请日：1995-11-27

申请人： Andrea Baroni ,  Giovanni Mastrodomenico ,  Michele Taliercio ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

发明人： Andrea Baroni ,  Giovanni Mastrodomenico ,  Michele Taliercio ,  Piero Capocelli ,  Luigi Carro ,  Rajamohan Varambally

IPC分类号： G06F17/50 ,  G11C7/14 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/14

摘要： A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

摘要翻译： 单端口RAM生成器架构，用于在CAD环境中生成不同的RAM结构，并测试不同RAM结构的操作能力。该架构包括一个静态RAM矩阵和一个自定时架构，其中包括一个控制逻辑 ，具有分别具有所述矩阵的字线和位列的等效负载的虚拟行和虚拟列。 虚拟列以比相应位列更快的速率放电，优化定时并降低功耗。 不同的列复用器选择为选定的RAM大小提供不同的RAM，每个RAM具有略微不同的硅面积和时序性能。

公开(公告)号：US5140542A

公开(公告)日：1992-08-18

申请号：US531719

申请日：1990-06-01

申请人： Michele Taliercio ,  Mario Lavorgna ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

发明人： Michele Taliercio ,  Mario Lavorgna ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

IPC分类号： G06F17/14 ,  G06F17/16

CPC分类号： G06F17/14 ,  G06F17/16

摘要： A method for the arithmetical calculation of two-dimensional transforms including two time steps of multiplication and accumulation, of which the first step is assigned to the product of the data and of the coefficient matrices and the second step is assigned to the subsequent product by the transposed coefficient matrix. Moreover, preferably the data to be transformed and the corresponding coefficients are supplied to a first multiplication step in time succession, possibly after their storage in an appropriate memory. The device for the attainment of the method includes two multipliers with their corresponding accumulator, a random-access type memory for storing the data to be transformed and the transform coefficients, a multiplexer which receives the data first from the input and then from the memory and arranges them in a time succession for the supply to a first multiplier, and a shift register which receives the transform coefficients from the memory and arranges them for the supply to the second multiplier.