公开(公告)号：US5138200A

公开(公告)日：1992-08-11

申请号：US423288

申请日：1989-10-18

申请人： Andrea Barsanti ,  Claudio Diazzi ,  Fabio Vio

发明人： Andrea Barsanti ,  Claudio Diazzi ,  Fabio Vio

IPC分类号： H03K5/02 ,  G01R29/12 ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K17/063

摘要： This device for generating a reference voltage for a capacitive bootstrap circuit of an output stage can be easily integrated. The output stage comprises a driving block, a capacitive bootstrap circuit and a reference voltage generating block generating a floating reference voltage which is referred to the output voltage signal and switches in accordance thereto.

公开(公告)号：USRE35745E

公开(公告)日：1998-03-17

申请号：US395135

申请日：1995-02-27

申请人： Andrea Barsanti ,  Claudio Diazzi ,  Fabio Vio

发明人： Andrea Barsanti ,  Claudio Diazzi ,  Fabio Vio

IPC分类号： H03K17/06 ,  H03K17/10

CPC分类号： H03K17/063

摘要： This device for generating a reference voltage for a capacitive bootstrap circuit of an output stage can be easily integrated. The output stage comprises a driving block, a capacitive bootstrap circuit and a reference voltage generating block generating a floating reference voltage which is referred to the output voltage signal and switches in accordance thereto.

公开(公告)号：US5146109A

公开(公告)日：1992-09-08

申请号：US736003

申请日：1991-07-25

申请人： Fabrizio Martignoni ,  Claudio Diazzi ,  Albino Pidutti ,  Fabio Vio

发明人： Fabrizio Martignoni ,  Claudio Diazzi ,  Albino Pidutti ,  Fabio Vio

IPC分类号： H03K17/567 ,  H03K3/356 ,  H03K17/687 ,  H03K19/0185

CPC分类号： H03K3/35613 ,  H03K3/356034

摘要： A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (I.sub.BIAS), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective loads for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.

公开(公告)号：US5160854A

公开(公告)日：1992-11-03

申请号：US734911

申请日：1991-07-24

申请人： Fabrizio Martignoni ,  Claudio Diazzi ,  Albino Pidutti ,  Fabio Vio

发明人： Fabrizio Martignoni ,  Claudio Diazzi ,  Albino Pidutti ,  Fabio Vio

IPC分类号： H03K17/04 ,  H03K17/0412 ,  H03K17/06 ,  H03K17/687 ,  H03K19/0185

CPC分类号： H03K17/06 ,  H03K17/04123 ,  H03K17/063

摘要： A level shifter, particularly suited for driving power stages for supplying power to integrated circuits, includes a DMOS transistor (40) which is driven by a digital signal source (42) and has a load resistor (44) as its drain load. A shifted output signal develops at the ends of said load resistor. The drain (V1) of the DMOS transistor is connected to the input of an inverter (46), while a Zener diode (54) and a second transistor (52) are connected in parallel with the load resistor (44), the gate of the second transistor (52) being driven by the output of the inverter (46). The output of the inverter (46) can be connected to the input of a drive stage (48), the output of which drives a power stage (50) for supplying power to an integrated circuit.