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公开(公告)号：US20130138931A1
公开(公告)日：2013-05-30
申请号：US13304885
申请日：2011-11-28
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3855 , G06F9/3861
摘要： A processor and method for maintaining the integrity of an execution return address stack (RAS). The execution RAS is maintained in an accurate state by storing information regarding branch instructions in a branch information table. The first time a branch instruction is executed, an entry is allocated and populated in the table. If the branch instruction is re-executed, a pointer address is retrieved from the corresponding table entry and the execution RAS pointer is repositioned to the retrieved pointer address. The execution RAS can also be used to restore a speculative RAS due to a mis-speculation.
摘要翻译： 一种用于维护执行返回地址堆栈（RAS）的完整性的处理器和方法。 通过在分支信息表中存储有关分支指令的信息，将执行RAS维持在准确的状态。 第一次执行分支指令时，会在表中分配并填充一个条目。 如果分支指令被重新执行，则从对应的表条目检索指针地址，并且将执行RAS指针重新定位到检索的指针地址。 执行RAS也可以用于恢复由于错误猜测而导致的投机RAS。
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公开(公告)号：US09354886B2
公开(公告)日：2016-05-31
申请号：US13304885
申请日：2011-11-28
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3855 , G06F9/3861
摘要： A processor and method for maintaining the integrity of an execution return address stack (RAS). The execution RAS is maintained in an accurate state by storing information regarding branch instructions in a branch information table. The first time a branch instruction is executed, an entry is allocated and populated in the table. If the branch instruction is re-executed, a pointer address is retrieved from the corresponding table entry and the execution RAS pointer is repositioned to the retrieved pointer address. The execution RAS can also be used to restore a speculative RAS due to a mis-speculation.
摘要翻译： 一种用于维护执行返回地址堆栈（RAS）的完整性的处理器和方法。 通过在分支信息表中存储有关分支指令的信息，将执行RAS维持在准确的状态。 第一次执行分支指令时，会在表中分配并填充一个条目。 如果分支指令被重新执行，则从对应的表条目检索指针地址，并且将执行RAS指针重新定位到检索的指针地址。 执行RAS也可以用于恢复由于错误猜测而导致的投机RAS。
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3.发明授权Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresis 有权防止具有交替模式滞后的分支指令的具有不匹配的第二预测器的第一预测器的更新训练公开(公告)号：US08959320B2
公开(公告)日：2015-02-17
申请号：US13313691
申请日：2011-12-07
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： A system and method for efficient branch prediction. A processor includes two branch predictors. A first branch predictor generates branch prediction data, such as a branch direction and a branch target address. The second branch predictor generates branch prediction data at a later time and with higher prediction accuracy. Control logic may determine whether the branch prediction data from each of the first and the second branch predictors match. If a mismatch occurs, the first predictor may be trained with the branch prediction data generated by the second branch predictor. A stored indication of hysteresis may indicate a given branch instruction exhibits a frequently alternating pattern regarding its branch direction. Such behavior may lead to consistent branch mispredictions due to the training is unable to keep up with the changing branch direction. When such a condition is determined to occur, the control logic may prevent training of the first predictor.
摘要翻译： 一种有效的分支预测的系统和方法。 处理器包括两个分支预测器。 第一分支预测器生成分支预测数据，例如分支方向和分支目标地址。 第二分支预测器在稍后的时间产生分支预测数据并具有更高的预测精度。 控制逻辑可以确定来自第一和第二分支预测器中的每一个的分支预测数据是否匹配。 如果发生不匹配，则可以利用由第二分支预测器产生的分支预测数据训练第一预测器。 存储的滞后指示可以指示给定的分支指令表现出关于其分支方向的频繁交替模式。 这种行为可能导致由于训练而导致的分支错误预测不能跟上分支方向的变化。 当确定发生这种情况时，控制逻辑可以防止第一预测器的训练。
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公开(公告)号：US20130151823A1
公开(公告)日：2013-06-13
申请号：US13313691
申请日：2011-12-07
CPC分类号： G06F9/3848
摘要： A system and method for efficient branch prediction. A processor includes two branch predictors. A first branch predictor generates branch prediction data, such as a branch direction and a branch target address. The second branch predictor generates branch prediction data at a later time and with higher prediction accuracy. Control logic may determine whether the branch prediction data from each of the first and the second branch predictors match. If a mismatch occurs, the first predictor may be trained with the branch prediction data generated by the second branch predictor. A stored indication of hysteresis may indicate a given branch instruction exhibits a frequently alternating pattern regarding its branch direction. Such behavior may lead to consistent branch mispredictions due to the training is unable to keep up with the changing branch direction. When such a condition is determined to occur, the control logic may prevent training of the first predictor.
摘要翻译： 一种有效的分支预测的系统和方法。 处理器包括两个分支预测器。 第一分支预测器生成分支预测数据，例如分支方向和分支目标地址。 第二分支预测器在稍后的时间产生分支预测数据并具有更高的预测精度。 控制逻辑可以确定来自第一和第二分支预测器中的每一个的分支预测数据是否匹配。 如果发生不匹配，则可以利用由第二分支预测器产生的分支预测数据训练第一预测器。 存储的滞后指示可以指示给定的分支指令表现出关于其分支方向的频繁交替模式。 这种行为可能导致由于训练而导致的分支错误预测不能跟上分支方向的变化。 当确定发生这种情况时，控制逻辑可以防止第一预测器的训练。
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5.发明授权公开(公告)号：US09280352B2
公开(公告)日：2016-03-08
申请号：US13307969
申请日：2011-11-30
申请人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
发明人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
CPC分类号： G06F9/3836 , G06F9/22 , G06F9/28 , G06F9/30145 , G06F9/3017 , G06F9/3814
摘要： An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
摘要翻译： 一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。 先行指针扫描调度队列的最新条目以获取微代码指令。 检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。 然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。
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公开(公告)号：US09367471B2
公开(公告)日：2016-06-14
申请号：US13609236
申请日：2012-09-10
CPC分类号： G06F12/0886 , G06F9/3802 , G06F9/3804 , G06F2212/452 , Y02D10/13
摘要： Various techniques for predicting instruction fetch widths. In one embodiment, a fetch prediction unit in a processor is configured to generate a fetch width that specifies a number of bits to be retrieved in a subsequent fetch from an instruction cache. The fetch prediction unit may also generate a fetch prediction that includes the fetch width in response to a current fetch request. A number of bits corresponding to the fetch width may be fetched from the instruction cache. The fetch width may correspond to a location of a predicted-taken control transfer instruction. This fetch width prediction may lead to power savings in instruction cache accesses.
摘要翻译： 用于预测指令获取宽度的各种技术。 在一个实施例中，处理器中的获取预测单元被配置为生成指定宽度，该宽度指定在从指令高速缓存中的随后取出中要检索的位数。 提取预测单元还可以响应于当前提取请求生成包括获取宽度的提取预测。 可以从指令高速缓冲存储器取出对应于取出宽度的位数。 获取宽度可以对应于预测的控制传送指令的位置。 这种获取宽度预测可能导致指令高速缓存访问中的功率节省。
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公开(公告)号：US20130138924A1
公开(公告)日：2013-05-30
申请号：US13307969
申请日：2011-11-30
申请人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
发明人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
IPC分类号： G06F9/22
CPC分类号： G06F9/3836 , G06F9/22 , G06F9/28 , G06F9/30145 , G06F9/3017 , G06F9/3814
摘要： An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
摘要翻译： 一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。 先行指针扫描调度队列的最新条目以获取微代码指令。 检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。 然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。
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公开(公告)号：US20140075156A1
公开(公告)日：2014-03-13
申请号：US13609236
申请日：2012-09-10
IPC分类号： G06F9/312
CPC分类号： G06F12/0886 , G06F9/3802 , G06F9/3804 , G06F2212/452 , Y02D10/13
摘要： Various techniques for predicting instruction fetch widths. In one embodiment, a fetch prediction unit in a processor is configured to generate a fetch width that specifies a number of bits to be retrieved in a subsequent fetch from an instruction cache. The fetch prediction unit may also generate a fetch prediction that includes the fetch width in response to a current fetch request. A number of bits corresponding to the fetch width may be fetched from the instruction cache. The fetch width may correspond to a location of a predicted-taken control transfer instruction. This fetch width prediction may lead to power savings in instruction cache accesses.
摘要翻译： 用于预测指令获取宽度的各种技术。 在一个实施例中，处理器中的获取预测单元被配置为生成指定宽度，该宽度指定在从指令高速缓存中的随后取出中要检索的位数。 提取预测单元还可以响应于当前提取请求生成包括获取宽度的提取预测。 可以从指令高速缓冲存储器取出对应于取出宽度的位数。 获取宽度可以对应于预测的控制传送指令的位置。 这种获取宽度预测可能导致指令高速缓存访问中的功率节省。
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