-
公开(公告)号：US20240362020A1
公开(公告)日：2024-10-31
申请号：US18532502
申请日：2023-12-07
发明人： Shawn Rosti , Timothy P. Finkbeiner
IPC分类号： G06F9/26 , G06F9/22 , G06F9/28 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/261 , G06F9/226 , G06F9/28 , G06F9/30145 , G06F9/30185 , G06F12/0875 , G06F15/7821 , G06F2212/452
摘要： The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.
-
2.发明公开公开(公告)号：US20240201986A1
公开(公告)日：2024-06-20
申请号：US18287193
申请日：2021-04-22
发明人： Tomoya YOKONO , Yoshiro YAMABE , Teruaki ISHIZAKI
CPC分类号： G06F9/28 , G06F9/3001 , G06F9/30043 , G06F9/45558 , G06F2009/45591
摘要： An accelerator control system includes an accelerator control device and an accelerator, wherein the accelerator control device includes first processing circuitry configured to store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator, and determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and the accelerator includes second processing circuitry configured to acquire the control data from the storage, perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator included in the acquired control data, and store the control data in the storage when the arithmetic processing is completed.
-
公开(公告)号：US11599497B2
公开(公告)日：2023-03-07
申请号：US17008363
申请日：2020-08-31
申请人： Intel Corporation
发明人： Zuoguo Wu , Debendra Das Sharma , Mohiuddin M. Mazumder , Jong-Ru Guo , Anupriya Sriramulu , Narasimha Lanka , Timothy Wig , Jeff Morriss
IPC分类号： G06F15/173 , H01L23/522 , H03K19/17736 , G06F15/16 , H01L21/768 , G06F9/28
摘要： A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.
-
公开(公告)号：US11488378B2
公开(公告)日：2022-11-01
申请号：US15728216
申请日：2017-10-09
发明人： Paul Dlugosch
IPC分类号： G06F9/44 , G06V10/94 , G06N20/00 , G06F9/28 , G06F9/445 , G06F9/448 , G06F9/455 , G06F15/78 , G06F15/173
摘要： Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can comprise a plurality of layers, where each layer performs an analysis on input data and provides an output based on the analysis. The output from lower layers in the hierarchical structure can be provided as inputs to higher layers. In this manner, lower layers can perform a lower level of analysis (e.g., more basic/fundamental analysis), while a higher layer can perform a higher level of analysis (e.g., more complex analysis) using the outputs from one or more lower layers. In an example, the hierarchical structure performs pattern recognition.
-
公开(公告)号：US20220092000A1
公开(公告)日：2022-03-24
申请号：US17280572
申请日：2019-07-18
发明人： Timo Reubold
摘要： A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.
-
公开(公告)号：US20220066775A1
公开(公告)日：2022-03-03
申请号：US17006968
申请日：2020-08-31
发明人： Xin Peng Liu , Yue Wang , Shuo Li , Xiaobo Wang
摘要： A method, computer program product, and system for managing parallel microservices are provided. The method may include identifying information pertaining to each of a plurality of target microservices to be invoked by an issuer microservice, a predefined condition associated with the plurality of target microservices, and an action to be executed by the issuer microservice in response to the predefined condition being satisfied. The method may also include sending a first request to available target microservices of the plurality of target microservices based on the information pertaining to the respective available target microservices. The method may also include, in response to receiving a response to the first request from an available target microservice of the available target microservices, determining whether the predefined condition is satisfied, and in response to determining that the predefined condition is satisfied, causing the action to be executed by the issuer microservice.
-
公开(公告)号：US11237974B2
公开(公告)日：2022-02-01
申请号：US16552001
申请日：2019-08-27
申请人： Arm Limited
IPC分类号： G06F12/0875 , G06F9/30 , G06F9/28
摘要： A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.
-
公开(公告)号：US11226126B2
公开(公告)日：2022-01-18
申请号：US15896726
申请日：2018-02-14
IPC分类号： G06F3/048 , F24F11/52 , F24F11/32 , F24F11/88 , H04L12/28 , G06F8/41 , G05B15/02 , G06F9/50 , F24F11/47 , G06F8/34 , G06F9/455 , G06F8/60 , G06F8/35 , G06F8/20 , H04L29/06 , H04L29/08 , G06F3/0481 , G06F3/0484 , G06F9/28 , G06F9/451 , G05B19/042 , G05B19/418 , G06F9/448 , H04L12/24 , G06F9/46
摘要： A method for generating and updating a live dashboard of a building management system for a building includes generating a dashboard designer interface and causing the dashboard designer interface to be displayed on a user device of a user, receiving a graphic element from the user, wherein the graphic file supports animation and user interaction, generating a widget by binding the graphic element received from the user to a widget of the live dashboard, binding a data point to the widget based on a user selection via the dashboard designer interface, wherein the data point being a data point of building equipment of the building, receiving a value for the data point from the building equipment, and displaying the widget in the live dashboard, the widget including an indication of the value for the data point.
-
公开(公告)号：US11041653B2
公开(公告)日：2021-06-22
申请号：US15896465
申请日：2018-02-14
发明人： Andrew J. Przybylski
IPC分类号： F24F11/00 , F24F11/52 , F24F11/32 , F24F11/88 , H04L12/28 , G06F8/41 , G05B15/02 , G06F9/50 , F24F11/47 , G06F8/34 , G06F9/455 , G06F8/60 , G06F8/35 , G06F8/20 , H04L29/06 , H04L29/08 , G06F3/0481 , G06F3/0484 , G06F9/28 , G06F9/451 , G05B19/042 , G05B19/418 , G06F9/448 , H04L12/24 , G06F9/46
摘要： A method for managing failures in multiple nodes of a building management system includes selecting a second building management system node from the building management system nodes to perform a computing job to determine one or more values for the building management system. The method includes sending the computing job to the second building management system node for the second building management system node to determine the one or more values for the building management system, receiving progress messages from the second building management system node, wherein the progress messages indicate the status of the second building management system node for determining the one or more values, and selecting a third building management system node from the plurality of building management system nodes to perform the computing job in response to the progress messages indicating that the second node has failed to determine the one or more values.
-
公开(公告)号：US11036890B2
公开(公告)日：2021-06-15
申请号：US16433888
申请日：2019-06-06
申请人： AWARE, INC.
发明人： Steven Kolk , Louis Scott Hills
IPC分类号： G06F9/50 , G06F9/28 , G06F21/83 , G06F21/32 , G06F21/71 , G06Q20/40 , G06F8/36 , G06F9/445 , G06F21/31
摘要： Methods and computer systems execute biometric operations in parallel. The performance of a biometric operation includes receiving a job request to perform the biometric operation. The job request includes input data, identifies a database to be used in the performance of the biometric operation, and specifies a function to be performed. The biometric operation is restructured as one or more tasks. A number of entries in the database is assigned to each of the one or more tasks. An independent worker process is generated for each different core of the multi-core processor. Each task of the one or more tasks is assigned to one of the worker processes. Results produced by each worker process assigned one of the one or more tasks are collected. A result of the biometric operation based on the collected results is reported.
-
-
-
-
-
-
-
-
-
搜索结果
497 条记录 (耗时 0.027 秒)
